IFUPLAInterlockImpl.mesa
Copyright c 1984 by Xerox Corporation. All rights reserved.
Last edited by Curry, August 27, 1986 7:15:40 pm PDT
McCreight, May 13, 1986 6:12:28 pm PDT
DIRECTORY
Commander,
Dragon,
DragOpsCross,
IFUPLAInterlock,
IO,
PLAOps;
IFUPLAInterlockImpl: CEDAR PROGRAM
IMPORTS Commander, IO, PLAOps =
BEGIN OPEN IFUPLAInterlock, PLAOps;
InterlockPLA: PLAOps.PLA;
InterlockProc:   PROC[args: InterlockIn]  RETURNS[result: InterlockOut];
GenInterlockPLA: PROC = {
read2:   BoolExpr ← BE[m:[dPCmndIsRd2: TRUE], d:[dPCmndIsRd2:  TRUE]];
read3:   BoolExpr ← BE[m:[dPCmndRd3:  TRUE], d:[dPCmndRd3:  TRUE]];
ac2:   BoolExpr ← BE[m:[a1IsC2:   TRUE], d:[a1IsC2:   TRUE]];
bc2:   BoolExpr ← BE[m:[b1IsC2:   TRUE], d:[b1IsC2:   TRUE]];
ac3:   BoolExpr ← BE[m:[a1IsC3:    TRUE], d:[a1IsC3:   TRUE]];
bc3:   BoolExpr ← BE[m:[b1IsC3:   TRUE], d:[b1IsC3:   TRUE]];
kIsRtOp:  BoolExpr ← BE[m:[kIsRtOp1:   TRUE], d:[kIsRtOp1:   TRUE]];
fCtlIsRtOp: BoolExpr ← BE[m:[fCtlIsRtOp1:  TRUE], d:[fCtlIsRtOp1:  TRUE]];
cField2:  BoolExpr ← BE[m:[cIsField2:   TRUE], d:[cIsField2:   TRUE]];
cField3:  BoolExpr ← BE[m:[cIsField3:    TRUE], d:[cIsField3:   TRUE]];
isBubble2: BoolExpr ← BE[m:[condEffect2: VAL[LAST[IFUPLAMainControl.CondEffect]]],
d:[condEffect2: bubble]];
aluRtFromB: BoolExpr ← Not[ Or[ kIsRtOp, fCtlIsRtOp ]];
interlock2:  BoolExpr ← And[ read2, Or[ ac2, bc2, And[ fCtlIsRtOp, cField2 ]]];
interlock3:  BoolExpr ← Or[
Not[isBubble2],
And[ read3, Or[ ac3, bc3, And[ fCtlIsRtOp, cField3 ]]]
];
Pipe Interlock
= stage1BHold OR (DPReject AND stage1BHoldIfReject)
Set[s: interlock2, out: [stage1BHold:  TRUE ] ];
Set[s: interlock3, out: [stage1BHoldIfReject:  TRUE ] ];
Bypassing
eUAluLeftSrc1
Set[s:     ac2,
out:[eUAluLeftSrc1: rBus]];
Set[s: And[Not[ ac2],   ac3],
out:[eUAluLeftSrc1: cBus]];
Set[s: And[Not[ ac2], Not[ ac3]],
out:[eUAluLeftSrc1: aBus]];
eUAluRightSrc1
Set[s:   kIsRtOp,
out:[eUAluRightSrc1: kBus]];
Set[s: And[ fCtlIsRtOp,  cField2 -- , Not[read2] -- ],
out:[eUAluRightSrc1: rBus]];
Set[s: And[ fCtlIsRtOp, Or[Not[cField2] -- , read2 -- ], cField3],
out:[eUAluRightSrc1: cBus]];
Set[s: And[ fCtlIsRtOp, Or[Not[cField2] -- , read2 -- ], Not[cField3]],
out:[eUAluRightSrc1: fCtlReg]];
Set[s: And[ aluRtFromB,   bc2 -- , Not[read2] -- ],
out:[eUAluRightSrc1: rBus]];
Set[s: And[ aluRtFromB, Or[Not[bc2] -- ,  read2 -- ],  bc3],
out:[eUAluRightSrc1: cBus]];
Set[s: And[ aluRtFromB, Or[Not[bc2] -- ,  read2 -- ], Not[bc3]],
out:[eUAluRightSrc1: bBus]];
eUStore2ASrc1
Set[s: And[  bc2 -- ,  Not[read2] -- ],
out:[eUStore2ASrc1: rBus]];
Set[s: And[  Or[Not[bc2] -- ,  read2 -- ],  bc3],
out:[eUStore2ASrc1: cBus]];
Set[s: And[  Or[Not[bc2] -- ,  read2 -- ], Not[bc3]],
out:[eUStore2ASrc1: bBus]];
eUSt3AIsCBus1
Set[s:    bc2,
out:[eUSt3AIsCBus1:  TRUE]];
};
BE: PROC [m, d: InterlockIn] RETURNS[BoolExpr] = {
mRef:  REF InterlockIn ← NARROW[InterlockPLA.mask];
dRef:  REF InterlockIn ← NARROW[InterlockPLA.data];
mRef^ ← m; dRef^ ← d; RETURN[GetBEForDataMask[InterlockPLA]]};
Set: PROC [s: BoolExpr ← NIL, m, d: InterlockIn ← [ ], out: InterlockOut] = {
res: REF InterlockOut ← NARROW[InterlockPLA.out];
IF s=NIL
THEN s ←      BE[m,d]
ELSE s ←   And[s, BE[m,d] ];
res^ ← out; SetOutForBE[InterlockPLA, s]};
GenInterlock: Commander.CommandProc = {
InterlockPLA ← NewPLA["IFUPLAInterlock.InterlockIn", "IFUPLAInterlock.InterlockOut", name];
GenInterlockPLA[];
[ ] ← ConvertTermListToCompleteSum[InterlockPLA.termList, FALSE, FALSE, cmd.out];
[ ] ← FindAMinimalCover[InterlockPLA.termList, 120, cmd.out];
WritePLAFile[InterlockPLA, NIL, cmd.out] };
doc: IO.ROPE = "Expects the name of the ttt file";
name: IO.ROPE = "IFUPLAInterlock";
Commander.Register[key:"GenInterlock",  proc: GenInterlock,  doc: doc];
END.