[Indigo]<Dragon7.0>IFUChipTest>IFUChipTestReset.mesa!2

IFUChipTestReset.mesa

Don Curry April 2, 1987 10:51:08 am PST

DIRECTORY

Core, Dragon, ICTest, IFUPublic, Ports, Rope, RosemaryUser;

IFUChipTestReset: CEDAR PROGRAM

IMPORTS ICTest

= BEGIN

II: TYPE = IFUPublic.II;

QPh: TYPE = {A, ab, B, ba};

T: BOOL = TRUE;

F: BOOL = FALSE;

ifuChipTest: Rope.ROPE = "IFU Chip Test";

Cycle: PROC[p: Ports.Port, Eval: RosemaryUser.TestEvalProc] = {

ClockPh[A, p, Eval];

ClockPh[ab, p, Eval];

ClockPh[B, p, Eval];

ClockPh[ba, p, Eval]};

ClockPh: PROC[ph: QPh, p: Ports.Port, Eval: RosemaryUser.TestEvalProc] = {

p[ II[ PhA ].ORD ].b ← ph = A;

p[ II[ PhB ].ORD ].b ← ph = B;

Eval[]};

Reset: ICTest.TestProc = {

p[ II[ KBus ].ORD ].lc ← 0;

p[ II[ EUAluOp ].ORD ].c ← 0;

p[ II[ EUCondSel ].ORD ].c ← 0;

p[ II[ EUCondition ].ORD ].b ← F;

p[ II[ EURdFromPBus ].ORD ].b ← F;

p[ II[ EUWriteToPBus ].ORD ].b ← F;

p[ II[ UserMode ].ORD ].b ← F;

p[ II[ DPCmd ].ORD ].c ← 0;

p[ II[ DPReject ].ORD ].b ← TRUE;

p[ II[ DPFault ].ORD ].c ← 0;

p[ II[ IPData ].ORD ].lc ← 0;

p[ II[ IPCmdFetch ].ORD ].b ← F;

p[ II[ IPReject ].ORD ].b ← TRUE;

p[ II[ IPFaulting ].ORD ].b ← F;

p[ II[ DShA ].ORD ].b ← F;

p[ II[ DShB ].ORD ].b ← F;

p[ II[ DShRd ].ORD ].b ← F;

p[ II[ DShWt ].ORD ].b ← F;

p[ II[ DShIn ].ORD ].b ← F;

p[ II[ DShOut ].ORD ].b ← F;

p[ II[ Reset ].ORD ].b ← TRUE;

p[ II[ Reschedule ].ORD ].b ← F;

p[ II[ KBus ].ORD ].d ← none;

p[ II[ EUAluOp ].ORD ].d ← none;

p[ II[ EUCondSel ].ORD ].d ← none;

p[ II[ EURdFromPBus ].ORD ].d ← none;

p[ II[ EUWriteToPBus ].ORD ].d ← none;

p[ II[ UserMode ].ORD ].d ← none;

p[ II[ DPCmd ].ORD ].d ← none;

p[ II[ IPData ].ORD ].d ← none;

p[ II[ IPCmdFetch ].ORD ].d ← none;

p[ II[ DShOut ].ORD ].d ← none;

Cycle[p, Eval];

p[ II[ Reset ].ORD ].b ← FALSE;

Cycle[p, Eval];

p[ II[ KBus ].ORD ].d ← expect;

p[ II[ IPData ].ORD ].d ← expect;

p[ II[ EUAluOp ].ORD ].d ← expect;

p[ II[ EUCondSel ].ORD ].d ← expect;

p[ II[ EURdFromPBus ].ORD ].d ← expect;

p[ II[ EUWriteToPBus ].ORD ].d ← expect;

p[ II[ UserMode ].ORD ].d ← expect;

p[ II[ DPCmd ].ORD ].d ← expect;

p[ II[ IPCmdFetch ].ORD ].d ← expect;

p[ II[ DShOut ].ORD ].d ← expect;

p[ II[ KBus ].ORD ].lc ← 84848000H;

p[ II[ DPReject ].ORD ].b ← FALSE;

Cycle[p, Eval];

ClockPh[A, p, Eval]; ClockPh[ab, p, Eval];

p[ II[ IPReject ].ORD ].b ← FALSE;

ClockPh[B, p, Eval]; ClockPh[ab, p, Eval];

p[ II[ EUAluOp ].ORD ].c ← Dragon.ALUOps[UAdd].ORD;

p[ II[ IPCmdFetch ].ORD ].b ← TRUE;

p[ II[ IPData ].ORD ].lc ← 0004041CH;

ClockPh[A, p, Eval]; ClockPh[ab, p, Eval];

p[ II[ IPData ].ORD ].lc ← 0D703E400H;

ClockPh[B, p, Eval]; ClockPh[ab, p, Eval];

Cycle[p, Eval];

Cycle[p, Eval]};

ICTest.RegisterTestProc[ifuChipTest, "Reset", Reset];

END.

ClockPh[A, p, Eval]; ClockPh[ab, p, Eval];