DIRECTORY CMosB, CoreClasses, CoreCreate, CoreFlat, CoreIO, CoreProperties, Dragon, EU, EUArith, EUInner, EUUtils, EUPadFrame, Ports, PWCore, Rosemary, Sisyph; EUImpl: CEDAR PROGRAM IMPORTS CoreClasses, CoreCreate, CoreFlat, CoreIO, CoreProperties, EUArith, EUInner, EUUtils, EUPadFrame, Ports, PWCore, Rosemary EXPORTS EU = BEGIN OPEN EU, CoreCreate; public: Wire _ EUUtils.GenWiresForBonnie[]; EUName: ROPE = Rosemary.Register[roseClassName: "EU", init: EUInit, evalSimple: EUSimple]; AssertionFailed: SIGNAL [message: ROPE] = CODE; MoreThanOne: PROC [a, b, c, d: BOOL _ FALSE] RETURNS [BOOL _ FALSE] ~ { BtoN: PROC [b: BOOL] RETURNS [NAT] ~ {RETURN[IF b THEN 1 ELSE 0]}; RETURN[BtoN[a]+BtoN[b]+BtoN[c]+BtoN[d]>1]; }; CreateEU: PUBLIC PROC [ typeData: REF EUTypeData _ NIL, fullEU: BOOL _ FALSE, useCkPt: BOOL _ FALSE] RETURNS [ cellType: CellType ] = { props: Properties _ CoreProperties.Props[[$ClusterInfo, typeData]]; SELECT TRUE FROM ~fullEU => cellType _ CoreClasses.CreateUnspecified[public, EUName, props]; fullEU AND ~useCkPt => { cellType _ EUUtils.Fetch["EU"]; IF cellType=NIL THEN { cellType _ CreateFullEU[EUUtils.GetContext[], props]; EUUtils.Store["EU", cellType]; }}; ENDCASE => cellType _ CoreIO.RestoreCellType[EUName]; CoreProperties.PutCellTypeProp[cellType, $ClusterInfo, typeData]; Ports.InitPorts[cellType, lc, none, "DPData", "KBus"]; Ports.InitPorts[cellType, c, none, "EUAluOp2AB", "EUCondSel2AB"]; Ports.InitPorts[cellType, b, drive, "EUCondition2B", "DShOut"]; [] _ Rosemary.BindCellType[cellType: cellType, roseClassName: EUName]; [] _ CoreFlat.CellTypeCutLabels[cellType, "EU"]; }; EUInit: Rosemary.InitProc = { state: EUState _ NEW[EUStateRec -- [ nRegs ] -- ]; {OPEN state; [Vdd, Gnd, PadVdd, PadGnd, PhA, PhB, DPRejectB, DPData] _ Ports.PortIndexes[cellType.public, "Vdd", "Gnd", "PadVdd", "PadGnd", "PhA", "PhB", "DPRejectB", "DPData"]; [KBus, EURdFromPBus3AB, EUWriteToPBus3AB, EUAluOp2AB, EUCondSel2AB, EUCondition2B] _ Ports.PortIndexes[cellType.public, "KBus", "EURdFromPBus3AB", "EUWriteToPBus3AB", "EUAluOp2AB", "EUCondSel2AB", "EUCondition2B"]; [DShA, DShB, DShRd, DShWt, DShIn, DShOut, DHold, DStAd] _ Ports.PortIndexes[cellType.public, "DShA", "DShB", "DShRd", "DShWt", "DShIn", "DShOut", "DHold", "DStAd"]; data _ NARROW[CoreProperties.GetCellTypeProp[cellType, $ClusterInfo]]; FOR i: NAT IN [0..nRegs) DO ram[i] _ 0 ENDLOOP; ram[EUUtils.constAdr+1] _ 1; ram[EUUtils.constAdr+2] _ 2; ram[EUUtils.constAdr+3] _ 3; }; stateAny _ state; }; EUSimple: Rosemary.EvalProc = { ShiftByOne: PROC [bIn: BOOL, shRegA, shRegB: CARD] RETURNS [newShRegA: CARD] ~ { newShRegA _ 2*shRegB + (IF bIn THEN 1 ELSE 0); -- very, very ugly }; Assert: PROC [condition: BOOL, message: ROPE _ NIL] = {IF NOT condition THEN SIGNAL AssertionFailed[message]}; state: EUState _ NARROW[stateAny]; {OPEN state; aAdr, bAdr, cAdr: CARD; -- actually, only bytes lSrc, rSrc, stSrc: NAT; st3IsC: BOOL; p[KBus].d _ p[DPData].d _ none; SELECT TRUE FROM p[DShRd].b => { regAd: NAT _ p[DStAd].c; shRegA _ reg[regAd]; }; p[DShWt].b => { regAd: NAT _ p[DStAd].c; reg[regAd] _ shRegB; }; p[DShA].b => shRegA _ ShiftByOne[p[DShIn].b, shRegA, shRegB]; p[DShB].b => { shRegB _ shRegA; p[DShOut].b _ EUArith.EBFLC[shRegB, 0]; }; ENDCASE => NULL; IF p[PhA].b THEN { cAdrInRAM: CARD; -- different from cAdr in case of reject cBusVal: CARD _ IF NOT rejectBA AND readPBusBA THEN reg[dataIn] ELSE reg[r3B]; [aAdr, bAdr, cAdr, st3IsC, lSrc, rSrc, stSrc] _ EUArith.ExplodeKReg[reg[kReg]]; cAdrInRAM _ IF rejectBA THEN EUUtils.marAdr ELSE cAdr; -- force address on reject IF cAdr=EUUtils.IFUAdr THEN {p[KBus].d _ drive; p[KBus].lc _ cBusVal}; IF cAdrInRAM IN [EUUtils.stackAdr .. EUUtils.bogusAdr) THEN ram[cAdrInRAM] _ cBusVal ELSE Assert[FALSE, "EU cAdr out of range"]; IF cAdr # EUUtils.junkAdr THEN { IF data # NIL AND data.noteStore # NIL AND NOT data.storeNoted THEN { data.noteStore[data: data.data, reg: cAdrInRAM, value: cBusVal]; data.storeNoted _ TRUE; }; }; IF ~rejectBA AND ~conditionBA THEN carryAB _ carryBA; IF ~rejectBA THEN { IF cAdr=EUUtils.fieldAdr THEN reg[field] _ cBusVal; reg[left] _ SELECT Dragon.ALULeftSources[VAL[lSrc]] FROM aBus => ram[aAdr], rBus => reg[r2B], cBus => cBusVal, ENDCASE => ERROR; reg[right] _ SELECT Dragon.ALURightSources[VAL[rSrc]] FROM bBus => ram[bAdr], rBus => reg[r2B], cBus => cBusVal, kBus => p[KBus].lc, fCtlReg => reg[field], ENDCASE => ERROR; reg[st2A] _ SELECT Dragon.Store2ASources[VAL[stSrc]] FROM bBus => ram[bAdr], cBus => cBusVal, rBus => reg[r2B], ENDCASE => ERROR; reg[r3A] _ reg[r2B]; reg[st3A] _ IF st3IsC THEN cBusVal ELSE reg[st2B]; p[DPData].d _ drive; -- Send address to Cache only once: the cache latches it. p[DPData].lc _ reg[r2B]; }; } ELSE IF data # NIL THEN data.storeNoted _ FALSE; IF p[PhB].b THEN { aluOut, fuOut: CARD; -- temporary overflow, c32, lz, ez, il: BOOL; aluOps: Dragon.ALUOps _ VAL[p[EUAluOp2AB].c]; rejectBA _ p[DPRejectB].b; readPBusBA _ p[EURdFromPBus3AB].b; reg[kReg] _ p[KBus].lc; Assert[NOT (p[EUWriteToPBus3AB].b AND p[EURdFromPBus3AB].b)]; reg[r3B] _ reg[r3A]; -- copy address reg[dataIn] _ p[DPData].lc; -- latch whatever comes from the pads IF p[EUWriteToPBus3AB].b THEN { p[DPData].d _ drive; p[DPData].lc _ reg[st3A] }; reg[st2B] _ reg[st2A]; [aluOut, c32, carryBA] _ EUArith.ALUOperation[aluOps, reg[left], reg[right], carryAB]; fuOut _ IF aluOps=FOP THEN EUArith.FieldOp[reg[left], reg[st2A], reg[right]] ELSE 0; reg[r2B] _ SELECT aluOps FROM BndChk => reg[left], FOP => fuOut, ENDCASE => aluOut; overflow _ ((c32 # EUArith.EBFLC[aluOut, 0]) # (EUArith.EBFLC[reg[left], 0] # EUArith.EBFLC[reg[right], 0])); lz _ (c32#(EUArith.EBFLC[reg[left], 0]#EUArith.EBFLC[reg[right], 0])); ez _ aluOut=0; il _ EUArith.LispTest[reg[left]] OR EUArith.LispTest[reg[right]] OR EUArith.LispTest[aluOut]; conditionBA _ SELECT Dragon.CondSelects[VAL[p[EUCondSel2AB].c]] FROM False => FALSE, EZ => ez, LZ => lz, -- VSub<0 LE => ez OR lz, -- VSub<=0, NE => ~ez, GE => ~lz, -- VSub>=0 GZ => ~(ez OR lz), -- VSub>0, OvFl => overflow, BC => ~c32, IL => il, -- the 3 high-order bits must be the same for both operands and result NotBC => c32, NotIL => ~il, ModeFault => TRUE, ENDCASE => ERROR Rosemary.Stop["Invalid EUCondition2B Code"]; p[EUCondition2B].b _ conditionBA; }; }}; globalPos: NAT _ 0; -- add the increment, then put the pad SetFirst: PROC [pos: NAT] = {globalPos _ pos}; Next: PROC [] RETURNS [NAT] = {RETURN[Move[1]]}; Move: PROC [delta: NAT] RETURNS [NAT] = { globalPos _ globalPos+delta; RETURN[globalPos]}; CreateFullEU: PROC [cx: Sisyph.Context, props: Properties _ NIL] RETURNS [cellType: CellType] = { vSize: NAT = 41; hSize: NAT = 50; left: NAT = 0; bottom: NAT = left+vSize; -- 41 right: NAT = bottom+hSize; -- 91 top: NAT = right+vSize; -- 132 pads: EUPadFrame.Pads _ NIL; dpData: Wire _ FindWire[public, "DPData"]; aluOp: Wire _ FindWire[public, "EUAluOp2AB"]; condSel: Wire _ FindWire[public, "EUCondSel2AB"]; kBus: Wire _ FindWire[public, "KBus"]; dStAd: Wire _ FindWire[public, "DStAd"]; onlyInternal: Wire _ WireList[LIST[ "phA", "phB", "nPhA", "nPhB", "enWrtPBusPhA", "enWrtPBusPhB", "enWrtIFUPhA", "enWrtIFUPhB", "condition", "writePBus", "readPBus3AB", "dpRejectB", Seq["aluOp", 4], Seq["condSel", 4], "shiftA", "shiftB", "read", "write", "shIn", "shOut", "hold", Seq["dStateAd", 4], Seq["fromIFU", 32], Seq["toIFU", 32], Seq["toPBus", 32], Seq["fromPBus", 32], "reject" ]]; -- just for routing SetFirst[left+10]; pads _ EUPadFrame.AddPad[pads, "DShA", $In, Next[], ["toChip", "shiftA"]]; -- new: 11 pads _ EUPadFrame.AddPad[pads, "Gnd", $Gnd, Next[]]; pads _ EUPadFrame.AddPad[pads, "DShB", $In, Next[], ["toChip", "shiftB"]]; pads _ EUPadFrame.AddPad[pads, "DShRd", $In, Next[], ["toChip", "read"]]; pads _ EUPadFrame.AddPad[pads, "PadGnd", $PadGnd, Next[]]; pads _ EUPadFrame.AddPad[pads, "DShWt", $In, Next[], ["toChip", "write"]]; pads _ EUPadFrame.AddPad[pads, "DShIn", $In, Next[], ["toChip", "shIn"]]; pads _ EUPadFrame.AddPad[pads, "PadVdd", $PadVdd, Next[]]; pads _ EUPadFrame.AddPad[pads, "DShOut", $Out, Next[], ["fromChip", "shOut"]]; pads _ EUPadFrame.AddPad[pads, "DHold", $In, Next[], ["toChip", "hold"]]; pads _ EUPadFrame.AddPad[pads, "Vdd", $Vdd, Next[]]; pads _ EUPadFrame.AddPad[pads, dStAd[0], $In, Next[], ["toChip", "dStateAd[0]"]]; pads _ EUPadFrame.AddPad[pads, dStAd[1], $In, Next[], ["toChip", "dStateAd[1]"]]; pads _ EUPadFrame.AddPad[pads, "Vdd", $Vdd, Next[]]; pads _ EUPadFrame.AddPad[pads, dStAd[2], $In, Next[], ["toChip", "dStateAd[2]"]]; pads _ EUPadFrame.AddPad[pads, dStAd[3], $In, Next[], ["toChip", "dStateAd[3]"]]; pads _ EUPadFrame.AddPad[pads, NIL, $Copyright, Next[]]; pads _ EUPadFrame.AddPad[pads, NIL, $Logo, Next[]]; pads _ EUPadFrame.AddPad[pads, NIL, $Name, Next[]]; SetFirst[bottom]; -- 41 FOR i: NAT IN [0..16) DO index: NAT _ 2*i; pads _ EUPadFrame.AddPad[pads, dpData[index], $IOTst, Move[2], -- s on 43 ["toChip", Index["fromPBus", index]], ["fromChip", Index["toPBus", index]], ["enWA", "enWrtPBusPhA"], ["enWB", "enWrtPBusPhB"]]; pads _ EUPadFrame.AddPad[pads, dpData[index+1], $IOTst, Next[], -- s on 44 ["toChip", Index["fromPBus", index+1]], ["fromChip", Index["toPBus", index+1]], ["enWA", "enWrtPBusPhA"], ["enWB", "enWrtPBusPhB"]]; ENDLOOP; SetFirst[bottom]; -- 42 pads _ EUPadFrame.AddPad[pads, "Gnd", $Gnd, Next[]]; -- v on 42 pads _ EUPadFrame.AddPad[pads, "PadVdd", $PadVdd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "Vdd", $Vdd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "PadVdd", $PadVdd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "PadGnd", $PadGnd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "Gnd", $Gnd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "PadGnd", $PadGnd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "PadVdd", $PadVdd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "Vdd", $Vdd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "PadVdd", $PadVdd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "PadGnd", $PadGnd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "Gnd", $Gnd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "PadGnd", $PadGnd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "PadVdd", $PadVdd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "Vdd", $Vdd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "PadVdd", $PadVdd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "Gnd", $Gnd, Move[3]]; SetFirst[right+8]; pads _ EUPadFrame.AddPad[pads, "PadGnd", $PadGnd, Next[]]; -- v on 100 pads _ EUPadFrame.AddPad[pads, "DPRejectB", $In, Next[], ["toChip", "dpRejectB"]]; pads _ EUPadFrame.AddPad[pads, "PhA", $Clk, Next[], ["Clock", "phA"], ["nClock", "nPhA"]]; pads _ EUPadFrame.AddPad[pads, "Gnd", $Gnd, Next[]]; pads _ EUPadFrame.AddPad[pads, "PhB", $Clk, Next[], ["Clock", "phB"], ["nClock", "nPhB"]]; pads _ EUPadFrame.AddPad[pads, "PadGnd", $PadGnd, Next[]]; -- former VRef pads _ EUPadFrame.AddPad[pads, "PadGnd", $PadGnd, Next[]]; pads _ EUPadFrame.AddPad[pads, "EUCondition2B", $Out, Next[], ["fromChip", "condition"]]; pads _ EUPadFrame.AddPad[pads, "EURdFromPBus3AB", $In, Next[], ["toChip", "readPBus3AB"]]; pads _ EUPadFrame.AddPad[pads, "PadVdd", $PadVdd, Next[]]; pads _ EUPadFrame.AddPad[pads, "EUWriteToPBus3AB", $In, Next[], ["toChip", "writePBus"]]; pads _ EUPadFrame.AddPad[pads, aluOp[0], $In, Next[], ["toChip", "aluOp[0]"]]; pads _ EUPadFrame.AddPad[pads, "Vdd", $Vdd, Next[]]; pads _ EUPadFrame.AddPad[pads, aluOp[1], $In, Next[], ["toChip", "aluOp[1]"]]; pads _ EUPadFrame.AddPad[pads, aluOp[2], $In, Next[], ["toChip", "aluOp[2]"]]; pads _ EUPadFrame.AddPad[pads, "PadVdd", $PadVdd, Next[]]; pads _ EUPadFrame.AddPad[pads, aluOp[3], $In, Next[], ["toChip", "aluOp[3]"]]; pads _ EUPadFrame.AddPad[pads, condSel[0], $In, Next[], ["toChip", "condSel[0]"]]; pads _ EUPadFrame.AddPad[pads, "PadGnd", $PadGnd, Next[]]; pads _ EUPadFrame.AddPad[pads, condSel[1], $In, Next[], ["toChip", "condSel[1]"]]; pads _ EUPadFrame.AddPad[pads, condSel[2], $In, Next[], ["toChip", "condSel[2]"]]; pads _ EUPadFrame.AddPad[pads, "Gnd", $Gnd, Next[]]; pads _ EUPadFrame.AddPad[pads, condSel[3], $In, Next[], ["toChip", "condSel[3]"]]; SetFirst[top]; -- 132 FOR i: NAT IN [0..16) DO index: NAT _ 31-2*i; pads _ EUPadFrame.AddPad[pads, kBus[index], $IOTst, Move[2], -- s on 134 ["toChip", Index["fromIFU", index]], ["fromChip", Index["toIFU", index]], ["enWA", "enWrtIFUPhA"], ["enWB", "enWrtIFUPhB"]]; -- EU never write on KBus during PhB pads _ EUPadFrame.AddPad[pads, kBus[index-1], $IOTst, Next[], -- s on 135 ["toChip", Index["fromIFU", index-1]], ["fromChip", Index["toIFU", index-1]], ["enWA", "enWrtIFUPhA"], ["enWB", "enWrtIFUPhB"]]; ENDLOOP; SetFirst[top]; -- 132 pads _ EUPadFrame.AddPad[pads, "Gnd", $Gnd, Next[]]; -- v on 133 pads _ EUPadFrame.AddPad[pads, "PadVdd", $PadVdd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "Vdd", $Vdd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "PadVdd", $PadVdd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "PadGnd", $PadGnd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "Gnd", $Gnd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "PadGnd", $PadGnd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "PadVdd", $PadVdd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "Vdd", $Vdd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "PadVdd", $PadVdd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "PadGnd", $PadGnd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "Gnd", $Gnd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "PadGnd", $PadGnd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "PadVdd", $PadVdd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "Vdd", $Vdd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "PadVdd", $PadVdd, Move[3]]; pads _ EUPadFrame.AddPad[pads, "Gnd", $Gnd, Move[3]]; cellType _ EUPadFrame.CreatePadFrame[ public: public, onlyInternal: onlyInternal, innerInstance: Instance[PWCore.RotateCellType[EUInner.CreateEUInner[cx], $Rot90], ["dStateAd", "dStateAd"], ["hold", "hold"], ["reject", "reject"] ], pads: pads, params: [ nbPadsX: hSize, nbPadsY: vSize, horizLayer: "metal2", vertLayer: "metal", centerDisplacement: [-200*CMosB.lambda, 0]], name: EUName, props: props ]; }; END. nEUImpl.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Louis Monier June 17, 1986 8:06:14 pm PDT McCreight, May 12, 1986 12:23:08 pm PDT Bertrand Serlet May 15, 1987 4:50:43 pm PDT Barth, April 19, 1986 5:25:00 pm PST Last Edited by: Louis Monier April 24, 1987 1:35:31 pm PDT -- shRegB[msb] goes out first -- DBus stuff Assert[NOT MoreThanOne[p[DShRd].b, p[DShWt].b, p[DShA].b, p[DShB].b], "DBus signals in illegal configuration"]; -- breaks the cluster simulation during reset -- PhA phase. Note that rejectBA alone inhibits almost any state change during PhA -- This instruction must be the first one of PhA! -- We select dataIn only in the case of a fetch without reject -- Updating the RAM addresses and various control bits; notice the role of reject -- On every PhA with RejectBA the faulty address is saved in ram[euMAR]; the EU generates the appropriate cAdrInRAM when RejectBA is sensed, so the rule is: we always write into the register file! -- I don't know who wrote this, so I treat it as a black box (LMM) -- PhiB phase. Most of the computations take place during PhB DPRejectB is valid at the end of PhiB but bogus on PhiA, so it must be latched on PhiB. -- Receive RAM addresses and control bits on KBus from IFU -- PBus: notice that in case of reject during a store, we keep sending the data even though it is useless; this could be changed if needed. -- Driving the PBus in case of a store -- Data pipe -- ALU computation -- FU computation -- Now pick up the result -- Condition and trap generation -- Left side -- Bottom side: msb(0) on the left -- Right side: msb(0) on the left -- Top side Κ €– "cedar" style˜codešœ ™ Kšœ Οmœ1™™>š œ žœžœžœ žœ ˜/Kšžœ ˜Kšžœ ˜J˜—Jš‘Q™QJšœO˜OJ™Jš‘Ε™ΕJšœ žœ žœžœ‘˜QKšžœžœ+˜FKšžœ žœ(žœ˜UKšžœžœ˜+J™Jš‘B™Bšžœžœ˜ šžœžœžœžœžœžœžœ˜EJšœ@˜@Jšœžœ˜J˜—J˜—J˜Jšžœ žœžœ˜5šžœ žœ˜Jšžœžœ˜3šœ žœžœž˜8Jšœ˜Jšœ˜Jšœ˜Jšžœžœ˜—šœ žœžœž˜:Jšœ˜Jšœ˜Jšœ˜Jšœ˜Jšœ˜Jšžœžœ˜—šœ žœžœ ž˜9Jšœ˜Jšœ˜Jšœ˜Jšžœžœ˜—Jšœ˜Jšœ žœžœ žœ ˜2Jšœ‘9˜NJšœ˜J˜—J˜—Jš žœžœžœžœžœ˜0J™Jš‘=™=šžœ žœ˜Jšœžœ‘ ˜!Jšœžœ˜ Jšœžœ˜-J˜JšœW™WJšœ˜Jšœ"˜"J˜Jš‘:™:Jšœ˜J˜Jš‘‹™‹Jšœžœžœ˜=Kšœ‘˜$Kšœ‘%˜AKš‘&™&šžœžœ˜Jšœ˜Jšœ˜J˜—Jš‘ ™ Jšœ˜J˜Jš‘™JšœV˜VJš‘™Jš œžœžœžœ3žœ˜TK™Kš‘™šœ žœž˜Kšœ˜Kšžœ ˜ Kšžœ ˜—J˜Jš‘ ™ Jšœžœžœžœ˜mJšœžœžœ˜FJšœ˜Jšœ!žœžœ˜]šœžœžœž˜DJšœ žœ˜Jšžœ ˜ Jšžœ ‘ ˜Jšžœ žœ‘ ˜Jšžœ ˜ Jšžœ ‘ ˜Jšžœ žœ‘ ˜Jšœ˜Jšžœ ˜Jšžœ ‘F˜RJšœ˜Jšœ˜Jšœžœ˜Jšžœžœ-˜=—Jšœ!˜!Jšœ˜—Kšœ˜—K˜Kšœ žœ‘&˜:Kš œžœžœ˜.Kš  œžœžœžœžœ ˜0š  œžœ žœžœžœ˜)Kšœ˜Kšžœ ˜K˜—š  œžœ*žœžœ˜aKšœžœ˜Kšœžœ˜Kšœžœ˜Kšœžœ‘˜Kšœžœ‘˜ Kšœžœ‘˜Kšœžœ˜K˜Kšœ*˜*Kšœ-˜-Kšœ1˜1Kšœ&˜&Kšœ(˜(šœžœ˜#Kšœ˜KšœK˜KKšœM˜MKšœQ˜QKšœM˜MKšœ ‘˜ —K™Kš‘ ™ Kšœ˜KšœK‘ ˜UKšœ4˜4KšœJ˜JKšœI˜IKšœ:˜:KšœJ˜JKšœI˜IKšœ:˜:KšœN˜NKšœI˜IKšœ4˜4KšœQ˜QKšœQ˜QKšœ4˜4KšœQ˜QKšœQ˜QKšœžœ˜8Kšœžœ˜3Kšœžœ˜3K™Kš‘"™"Kšœ‘˜šžœžœžœ ž˜Kšœžœ˜šœ@‘ ˜JKšœ&˜&Kšœ%˜%Kšœ˜Kšœ˜—šœA‘ ˜KKšœ(˜(Kšœ'˜'Kšœ˜Kšœ˜—Kšžœ˜—Kšœ‘˜Kšœ7‘ ˜AKšœ;˜;Kšœ5˜5Kšœ;˜;Kšœ;˜;Kšœ5˜5Kšœ;˜;Kšœ;˜;Kšœ5˜5Kšœ;˜;Kšœ;˜;Kšœ5˜5Kšœ;˜;Kšœ;˜;Kšœ5˜5Kšœ;˜;Kšœ5˜5K™Kš‘!™!Kšœ˜Kšœ<‘ ˜GKšœR˜RKšœZ˜ZKšœ4˜4KšœZ˜ZKšœ<‘˜JKšœ:˜:KšœY˜YKšœZ˜ZKšœ:˜:KšœY˜YKšœN˜NKšœ4˜4KšœN˜NKšœN˜NKšœ:˜:KšœN˜NKšœR˜RKšœ:˜:KšœR˜RKšœR˜RKšœ4˜4KšœR˜RK™Kš‘ ™ Kšœ‘˜šžœžœžœ ž˜Kšœžœ ˜šœ>‘ ˜IKšœ%˜%Kšœ$˜$Kšœ˜Kšœ‘$˜>—šœ?‘ ˜JKšœ'˜'Kšœ&˜&Kšœ˜Kšœ˜—Kšžœ˜—Kšœ‘˜Kšœ6‘ ˜AKšœ;˜;Kšœ5˜5Kšœ;˜;Kšœ;˜;Kšœ5˜5Kšœ;˜;Kšœ;˜;Kšœ5˜5Kšœ;˜;Kšœ;˜;Kšœ5˜5Kšœ;˜;Kšœ;˜;Kšœ5˜5Kšœ;˜;Kšœ5˜5K˜šœ%˜%Kšœ˜Kšœ˜šœQ˜QKšœC˜C—Kšœ ˜ šœ ˜ Kšœ˜Kšœ˜Kšœ˜Kšœ˜Kšœ,˜,—Kšœ ˜ Kšœ ˜ K˜—Kšœ˜—K˜Kšžœ˜K˜—…—6¦J”