EUStdPadFrameImpl.mesa
Copyright Ó 1985, 1986, 1987 by Xerox Corporation. All rights reserved.
Louis Monier March 11, 1987 12:59:02 pm PST
Last Edited by: Louis Monier March 11, 1987 6:23:04 pm PST
Bertrand Serlet May 15, 1987 4:57:07 pm PDT
DIRECTORY CMosB, CoreCreate, EUInner, EUUtils, EUPadFrame, CommonPGA176, PWCore, Sisyph;
EUStdPadFrameImpl: CEDAR PROGRAM
IMPORTS CoreCreate, EUInner, EUUtils, EUPadFrame, CommonPGA176, PWCore
EXPORTS EUInner =
BEGIN OPEN CoreCreate, CommonPGA176;
public: Wire ← EUUtils.GenWiresForBonnie[];
CreateFullEU: PUBLIC PROC [cx: Sisyph.Context, props: Properties ← NIL] RETURNS [cellType: CellType] = {
kBus: Wire ← FindWire[public, "KBus"];
dpData: Wire ← FindWire[public, "DPData"];
aluOp: Wire ← FindWire[public, "EUAluOp2AB"];
condSel: Wire ← FindWire[public, "EUCondSel2AB"];
dStAd: Wire ← FindWire[public, "DStAd"];
onlyInternal: Wire ← WireList[LIST[
"phA", "phB", "nPhA", "nPhB",
"enWrtPBusPhA", "enWrtPBusPhB", "enWrtIFUPhA", "condition",
"writePBus", "readPBus3AB", "dpRejectB", Seq["aluOp", 4], Seq["condSel", 4],
"shiftA", "shiftB", "read", "write", "shIn", "shOut", "hold", Seq["dStateAd", 4],
Seq["fromIFU", 32], Seq["toIFU", 32], Seq["toPBus", 32], Seq["fromPBus", 32],
"reject" ]]; -- just for routing
pga: PGADescr ← MakeCommonPGA176[]; -- this puts the power pads
-- Left side
SetPos[pga, pga176.left+9];
SPad[pga, "DShA",  $In, ["toChip", "shiftA"]];
SPad[pga, "DShB",  $In, ["toChip", "shiftB"]];
SPad[pga, "DShRd",  $In, ["toChip", "read"]];
SPad[pga, "DShWt",  $In, ["toChip", "write"]];
SPad[pga, "DShIn",  $In, ["toChip", "shIn"]];
SPad[pga, "DShOut",  $Out, ["fromChip", "shOut"]];
SPad[pga, "DHold",  $In, ["toChip", "hold"]];
SPad[pga, dStAd[0],  $In, ["toChip", "dStateAd[0]"]];
SPad[pga, dStAd[1],  $In, ["toChip", "dStateAd[1]"]];
SPad[pga, dStAd[2],  $In, ["toChip", "dStateAd[2]"]];
SPad[pga, dStAd[3],  $In, ["toChip", "dStateAd[3]"]];
SPad[pga, NIL,   $Copyright];
SPad[pga, NIL,   $Logo];
SPad[pga, NIL,   $Name];
-- Bottom side: msb(0) on the left
SetPos[pga, pga176.bottom];
FOR index: NAT IN [0..32) DO
SPad[pga, dpData[index], $IOTst,  
["toChip", Index["fromPBus", index]],
["fromChip", Index["toPBus", index]],
["enWA", "enWrtPBusPhA"],
["enWB", "enWrtPBusPhB"]];
ENDLOOP;
-- Right side: msb(0) on the left
SetPos[pga, pga176.right+8];
SPad[pga, "DPRejectB",  $In, ["toChip", "dpRejectB"]];
SPad[pga, "PhA",   $Clk, ["Clock", "phA"], ["nClock", "nPhA"]];
SPad[pga, "PhB",   $Clk, ["Clock", "phB"], ["nClock", "nPhB"]];
SPad[pga, "EUCondition2B",  $Out, ["fromChip", "condition"]];
SPad[pga, "EURdFromPBus3AB", $In, ["toChip", "readPBus3AB"]];
SPad[pga, "EUWriteToPBus3AB", $In, ["toChip", "writePBus"]];
SPad[pga, aluOp[0],  $In, ["toChip", "aluOp[0]"]];
SPad[pga, aluOp[1],  $In, ["toChip", "aluOp[1]"]];
SPad[pga, aluOp[2],  $In, ["toChip", "aluOp[2]"]];
SPad[pga, aluOp[3],  $In, ["toChip", "aluOp[3]"]];
SPad[pga, condSel[0],  $In, ["toChip", "condSel[0]"]];
SPad[pga, condSel[1],  $In, ["toChip", "condSel[1]"]];
SPad[pga, condSel[2],  $In, ["toChip", "condSel[2]"]];
SPad[pga, condSel[3],  $In, ["toChip", "condSel[3]"]];
-- Top side
SetPos[pga, pga176.top];
FOR index: NAT DECREASING IN [0..32) DO
SPad[pga, kBus[index], $IOTst,
["toChip", Index["fromIFU", index]],
["fromChip", Index["toIFU", index]],
["enWA", "enWrtIFUPhA"],
["enWB", "Gnd"]]; -- EU never write on KBus during PhB
ENDLOOP;
cellType ← EUPadFrame.CreatePadFrame[
public: public,
onlyInternal: onlyInternal,
innerInstance: Instance[PWCore.RotateCellType[EUInner.CreateEUInner[cx], $Rot90],
["dStateAd", "dStateAd"], ["hold", "hold"], ["reject", "reject"] ],
pads: pga.pads,
params: [
horizLayer: "metal2",
vertLayer: "metal",
nbPadsX: pga176.size,
nbPadsY: pga176.size,
library: "CommonPads.dale",
centerDisplacement: [-200*CMosB.lambda, 0]],
name: "EU",
props: props
];
};
END.