<> <> <> <<>> <<>> Model: a 2/16 transistor -> 1mA peak, 0.1mA average under normal load and 50ns cycle. <<>> Register file RamCell (4*32 h, 40 v) inv: 2*(16//4) v: Gnd: 8 per quad h: Vdd: 6, Gnd: 8 RamMux: only muxes RamRW inv: 16+16+8+32+64 v: Vdd: 40, Gnd: 32 h: Vdd: 40, Gnd: 40 During precharge, a bit-line is pulled-up by a 2/12 p device. The capacitance of a bit line is 1.5pF. The average intensity is 0.13mA. Datapath Any Register Register inv: 16+32 v: Vdd: 40 Gnd: 40 Tristate inv: 16+32+16 v: Vdd: 40 Gnd: 40 DBus Shift Register ShReg inv: 16+32+16+16 v: Vdd: 40 Gnd: 40 h: Vdd: 10 Gnd: 10 ALU ALUCP inv: 32+32+32+16+16+16 v: Vdd: 40 Gnd: 30 h: Vdd: 40 Gnd: 40 ALUFnBlock inv: 16+16+16 v: Vdd: 10 Gnd: 10 h: Vdd: 40 Gnd: 40 Field Unit Compose inv: 16 v: Vdd: 40 Gnd: 30 h: Vdd: 40 Gnd: 40 Mask generator inv: 8 v: Vdd: 30 Gnd: 30 Shifter inv: 8 v: Vdd: 40 Gnd: 30 PBus Driver PDriver inv: 8+8+16 v: Vdd: 40 Gnd: 40 h: Vdd: 8 Gnd: 8 Taking in to account PhA and PhB-type registers, the maximum pulse per column in the datapath is at most 30mA. With 4mm by 10lines, the drop is about 0.3V. Let's refine: below the ALU channel, lines are 3010the DBus shift register. The ALU fires out of sync with the regs, so the peak is 20mA. SC block
RamRW inv:
16+16+8+32+64 v: Vdd:
40, Gnd:
32 h: Vdd:
40, Gnd:
40
RamRW inv:
16+16+8+32+64 v: Vdd:
40, Gnd:
32 h: Vdd:
40, Gnd:
40 Ram Control
RamRW inv:
16+16+8+32+64 v: Vdd:
40, Gnd:
32 h: Vdd:
40, Gnd:
40
RamRW inv:
16+16+8+32+64 v: Vdd:
40, Gnd:
32 h: Vdd:
40, Gnd:
40 DP Control
RamRW inv:
16+16+8+32+64 v: Vdd:
40, Gnd:
32 h: Vdd:
40, Gnd:
40
RamRW inv:
16+16+8+32+64 v: Vdd:
40, Gnd:
32 h: Vdd:
40, Gnd:
40 Pads
RamRW inv:
16+16+8+32+64 v: Vdd:
40, Gnd:
32 h: Vdd:
40, Gnd:
40
RamRW inv:
16+16+8+32+64 v: Vdd:
40, Gnd:
32 h: Vdd:
40, Gnd:
40