<> <> <> <> <> <> <> <<>> DIRECTORY Core, Ports; <<>> EU: CEDAR DEFINITIONS = BEGIN CreateEU: PUBLIC PROC [typeData: REF EUTypeData _ NIL, fullEU: BOOL _ FALSE, useCkPt: BOOL _ FALSE] RETURNS [cellType: Core.CellType]; EUState: TYPE = REF EUStateRec; EUStateRec: TYPE = RECORD[ <<-- kitchen sink>> data: REF EUTypeData _ NIL, <<-- ports indexes>> Vdd, Gnd, PadVdd, PadGnd, PhA, PhB, DPRejectB, DPData, -- 32 bits KBus, -- 32 bits <<-- Phase-multiplexed on KBus>> <> <> <> <> <> <> <> EURdFromPBus3AB, EUWriteToPBus3AB, EUAluOp2AB, -- 4 bits Dragon.ALUOps EUCondSel2AB, -- 4 bits Dragon.CondSelects EUCondition2B, DShA, DShB, DShRd, DShWt, DShIn, DShOut, DHold, DStAd: NAT _ LAST[NAT], <<-- registers>> reg: ARRAY PipeRange OF CARD _ ALL[0], shRegA, shRegB: CARD _ 0, -- the data part of the DBus shift register op, dStateAd: NAT _ 0, -- the remainder of the shift register prevDShift, prevDExecute: Ports.Level _ X, -- the DShift clock is edge-triggered <<-- a few bits of state>> carryAB, carryBA: BOOL _ FALSE, conditionBA: BOOL _ FALSE, -- needed during A to update carryAB rejectBA: BOOL _ FALSE, -- a copy of DPRejectB stable during PhA readPBusBA: BOOL _ FALSE, -- a copy of EURdFromPBus3AB stable during the next PhA <<-- register file>> <> size: NAT _ nRegs, ram: ARRAY [0..nRegs) OF CARD ]; PipeRange: TYPE = [left..dataIn]; -- states <<-- pipeline registers indexes>> left: NAT = 0; right: NAT = 1; st2A: NAT = 2; st2B: NAT = 3; st3A: NAT = 4; kReg: NAT = 5; field: NAT = 6; r2B: NAT = 7; -- rBus r3A: NAT = 8; r3B: NAT = 9; -- cBus dataIn: NAT = 10; -- cBus EUTypeData: TYPE = RECORD [ data: REF ANY, storeNoted: BOOL, noteStore: NoteRegStoreProc _ NIL ]; NoteRegStoreProc: TYPE = PROC [ data: REF ANY, reg: [0..256), value: CARD ]; nRegs: NAT = 160; END.