Name format bytes Description
Addition
ADDB LB 2 [S] ← [S] + CARD.FromCARD8[a] + Carry; Carry ← 0; trap on overflow.
ADDDB LH 3 [S] ← [S] + CARD.FromCARD16[ab] + Carry; Carry ← 0; trap on overflow.
ADDQB LW 5 [S] ← [S] + abgd + Carry; Carry ← 0; trap on overflow.
ADD I 1 [S—1] ← [S—1] + [S] + Carry; Carry ← 0; DS ← DS — 1; trap on overflow.
RADD RRR 3 Rc ← Ra + Rb + Carry; Carry ← 0; trap on overflow.
QADD QR 2 Qd ← Qs + Rb + Carry; Carry ← 0; trap on overflow.
RUADD RRR 3 Rc ← Ra + Rb + Carry; Carry ← CarryOut.
RVADD RRR 3 Rc ← Ra + Rb.
Subtraction
SUBB LB 2 [S] ← [S] — CARD.FromCARD8[a] — Carry; Carry ← 0; trap on overflow.
SUBDB LH 3 [S] ← [S] — CARD.FromCARD16[ab] — Carry; Carry ← 0; trap on overflow.
SUBQB LW 5 [S] ← [S] — abgd — Carry; Carry ← 0; trap on overflow.
SUB I 1 [S—1] ← [S—1] — [S] — Carry; Carry ← 0; DS ← DS — 1; trap on overflow.
RSUB RRR 3 Rc ← Ra — Rb — Carry; Carry ← 0; trap on overflow.
QSUB QR 2 Qd ← Qs — Rb — Carry; Carry ← 0; trap on overflow.
RUSUB RRR 3 Rc ← Ra — Rb — Carry; Carry ← NOT[CarryOut].
RVSUB RRR 3 Rc ← Ra — Rb.
Bitwise Logical
AND I 1 [S—1] ← [S—1] AND [S]; DS ← DS — 1.
RAND RRR 3 Rc ← Ra AND Rb.
QAND QR 2 Qd ← Qs AND Rb.
OR I 1 [S—1] ← [S—1] OR [S]; DS ← DS — 1.
ROR RRR 3 Rc ← Ra OR Rb.
QOR QR 2 Qd ← Qs OR Rb.
RXOR RRR 3 Rc ← Ra XOR Rb.
Field Unit
SHL LH 3 [S] ← FieldUnit.Operate[[S], 0, <insert, width, shift>].
SHR LH 3 [S] ← FieldUnit.Operate[[S], [S], <insert, width, shift>].
SHDL LH 3 [S—1] ← FieldUnit.Operate[[S—1], [S], <insert, width, shift>]; DS ← DS — 1.
SHDR LH 3 [S—1] ← FieldUnit.Operate[[S], [S—1], <insert, width, shift>]; DS ← DS — 1.
FSDB LH 3 Field ← [S] + <insert, width, shift>; DS ← DS — 1.
RFU RRR 3 Rc ← FieldUnit.Operate[Ra, Rb, Field].
NoOps
J1 I 1 PC ← PC + 1.
J2 LB 2 PC ← PC + 2.
J3 LH 3 PC ← PC + 3.
J5 LW 5 PC ← PC + 5.
Constants
LIB LB 2 [S+1] ← CARD.FromCARD8[a]; DS ← DS + 1.
LIDB LH 3 [S+1] ← CARD.FromCARD16[ab]; DS ← DS + 1.
LIQB LW 5 [S+1] ← abgd; DS ← DS + 1.
LCm I 1 [S+1] ← Constants[m]; DS ← DS + 1.
Procedure Calls and Returns
LFC LH 3 IFUOps.Push[PC, L, mode, trapsEnabled, version]; PC ← PC + INT.FromINT16[ab].
DFC LW 5 IFUOps.Push[PC, L, mode, trapsEnabled, version]; PC ← abgd.
SFC I 1 IFUOps.Push[PC, L, mode, trapsEnabled, version]; PC ← [S]; DS ← DS — 1.
SFCI I 1 IFUOps.Push[PC, L, mode, trapsEnabled, version]; PC ← (S)^.
KFC I 1 IFUOps.Push[PC, L, mode, trapsEnabled, version]; mode ← kernel; PC ← InstTrap[KFC].
RETN I 1 [PC, L, mode, trapsEnabled, version] ← IFUOps.Pop[].
RET LB 2 S ← L + a; [PC, L, mode, trapsEnabled, version] ← IFUOps.Pop[].
Frame and Stack Pointers
DIS I 1 S ← S — 1.
AS LB 2 S ← S + a.
ASL LB 2 S ← L + a.
ALS LB 2 L ← S + a.
AL LB 2 L ← L + a.
Register Copies
DUP I 1 [S+1] ← [S]; DS ← DS + 1.
EXDIS I 1 [S—1] ← [S]; DS ← DS — 1.
LRn LR 1 [S+1] ← Locals[n]; DS ← DS + 1.
SRn LR 1 Locals[n] ← [S]; DS ← DS — 1.
Loads from Memory
RRX RRR 3 Rc ← (Ra + Rb)^.
QRX QR 2 Qd ← (Qs + Rb)^.
RB LB 2 [S] ← ([S] + CARD.FromCARD8[a])^.
RSB LB 2 [S+1] ← ([S] + CARD.FromCARD8[a])^; DS ← DS + 1.
RX I 1 [S—1] ← ([S—1] + [S])^; DS ← DS — 1.
LRIn XO 2 [S+1] ← (Locals[n] + CARD.FromCARD8[a])^; DS ← DS + 1.
RRI XRO 3 Locals[regA] ← (Locals[regB] + CARD.FromCARD8[b])^.
RAI XRO 3 Locals[regA] ← (Aux[regB] + CARD.FromCARD8[b])^.
LGF LH 3 [S+1] ← (AuxRegs[0] + CARD.FromCARD16[ab])^; DS ← DS + 1.
Stores to Memory
WB LB 2 ([S] + CARD.FromCARD8[a])^ ← [S—1]; DS ← DS — 2.
WSB LB 2 ([S—1] + CARD.FromCARD8[a])^ ← [S]; DS ← DS — 2.
PSB LB 2 ([S—1] + CARD.FromCARD8[a])^ ← [S]; DS ← DS — 1.
SRIn XO 2 (Locals[n] + CARD.FromCARD8[a])^ ← [S]; DS ← DS — 1.
WRI XRO 3 (Locals[regB] + CARD.FromCARD8[b])^ ← Locals[regA].
WAI XRO 3 (Aux[regB] + CARD.FromCARD8[b])^ ← Locals[regA].
CST LB 2 [S+1]𡤌Store[ptr: [S—2]+CARD.FromCARD8[a], new: [S—1], old: [S]]; DS ← DS + 1.
Unconditional Jumps
JB LB 2 PC ← PC + INT.FromINT8[a].
JDB LH 3 PC ← PC + INT.FromINT16[ab].
JQB LW 5 PC ← abgd.
JSD I 1 PC ← [S]; DS ← DS — 1.
JSR I 1 PC ← PC + [S]; DS ← DS — 1.
Conditional Jumps
JEBBj LBD 3 CARD.FromCARD8[a] = [S] Ò PC ← PC + INT.FromINT8[b]; DS ← DS — 1.
JNEBBj LBD 3 CARD.FromCARD8[a] # [S] Ò PC ← PC + INT.FromINT8[b]; DS ← DS — 1.
RJLBj RD 3 T < Rb Ò PC ← PC + INT.FromINT8[b].
RJLEBj RD 3 T <= Rb Ò PC ← PC + INT.FromINT8[b].
RJEBj RD 3 T = Rb Ò PC ← PC + INT.FromINT8[b].
RJNEBj RD 3 T # Rb Ò PC ← PC + INT.FromINT8[b].
RJGEBj RD 3 T >= Rb Ò PC ← PC + INT.FromINT8[b].
RJGBj RD 3 T > Rb Ò PC ← PC + INT.FromINT8[b].
Bounds Checks
RBC RRR 3 IF (Ra < Rb) THEN Rc ← Ra ELSE trap.
BC I 1 IF NOT([S—1] < [S]) THEN trap; DS ← DS — 1.
QBC QR 2 IF (Qs < Rb) THEN Qd ← Qs ELSE trap.
Lisp Instructions
LADD I 1 [S—1] ← [S] + [S—1]; Carry ← 0; DS ← DS — 1; trap on Lisp NaN.
QLADD QR 2 Qd ← Qs + Rb; Carry ← 0; trap on Lisp NaN.
RLADD RRR 3 Rc ← Ra + Rb; Carry ← 0; trap on Lisp NaN.
LSUB I 1 [S—1] ← [S—1] — [S]; Carry ← 0; DS ← DS — 1; trap on Lisp NaN.
QLSUB QR 2 Qd ← Qs — Rb; Carry ← 0; trap on Lisp NaN.
RLSUB RRR 3 Rc ← Ra — Rb. Carry ← 0; trap on Lisp NaN.
Input and Output
LIP LB 2 [S+1] ← ProcReg[a]; DS ← DS + 1.
SIP LB 2 ProcReg[a] ← [S]; DS ← DS — 1.
IOD LIO 3 IsRead[PCmd] Ò [S+1] ← Dispatch[Address, PCmd]; DS ← DS + 1;
IsWrite[PCmd] Ò Dispatch[Address, [S], PCmd]; DS ← DS — 1.
IODA LIO 3 IsRead[PCmd] Ò [S] ← Dispatch[Address+[S], PCmd];
IsWrite[PCmd] Ò Dispatch[Address+[S], [S—1], PCmd]; DS ← DS — 2.
ION LIO 3 IsRead[PCmd] Ò [S+1] ← Dispatch[Address, PCmd];
IsWrite[PCmd] Ò Dispatch[Address, [S], PCmd].
Formats
I Implicit opcode
LR Locals Register opcode
LB Literal Byte opcode a
LH Literal Halfword opcode a b
LW Literal Word opcode a b g d
RRR Registers to Register opcode acbA| Rb Rc | Ra
QR Quick Register opcode Q bA| Rb
RD Register Displacement opcode T bA| Rb b
LBD Literal Byte Displacement opcode a b
XO Index Register Offset opcode a
XRO Index Register Register Offset opcode a b
Notes
a is the byte after the opcode.
b is the second byte after the opcode.
ab is the double byte after the opcode.
abgd is the word after the opcode.
[S] is the top of the stack, i.e. Stack[S].
[S]— is the top of the stack popped after use, i.e. Stack[S], DS ← DS — 1.
[S—1] is the next to the top of the stack, i.e. Stack[S—1].
[S—1]— is the next to the top of the stack popped after use, i.e. Stack[S—1], DS ← DS — 1.
[S+1]+ is a push onto the stack, i.e. Stack[S+1], DS ← DS + 1.
DS is added to S after the instruction completes.
Constants[m] is one of the 12 constant registers.
Locals[n] is one of the 16 local registers.
AuxRegs[n] is one of the 16 auxiliary registers.
-- Locals[n] and AuxRegs[n] cannot be used in the same instruction.
Ra { Locals[n], Constants[m], [S], [S—1], [S]—, [S—1]— }.
Rb { Locals[n], Constants[m], [S], [S—1], [S]—, [S—1]— }.
Rc { Locals[n], Constants[m], [S], [S—1], [S+1]+ }.
T { [S], [S]—, Constants[0], Constants[1] }.
Q { [d: [S], s: [S]],
[d: [S+1]+, s: [S]],
[d: [S+1]+, s: Constants[0]],
[d: [S+1]+, s: Constants[1]] }.
For field unit instructions:
ab
:
MACHINE
DEPENDENT
RECORD [
pad0, pad1, pad2: Bit, -- must be 0.
insert: BOOLEAN, -- insert right-justified field from left into right.
width: CARDINAL [0..BitsPerWord],
shift: CARDINAL [0..BitsPerWord]
];
For conditional jump instructions:
j = ``J'' Ò predicted to jump; j = ``'' Ò predicted to fall through.