Dragon
Instruction Set Summary - Functional
Name form bytes Description
Addition
ADDB LB 2 [S] ← [S] + zExt[literal] + Carry; Carry ← 0; trap on overflow.
ADDDB LDB 3 [S] ← [S] + zExt[literal] + Carry; Carry ← 0; trap on overflow.
ADDQB LW 5 [S] ← [S] + zExt[literal] + Carry; Carry ← 0; trap on overflow.
ADD I 1 [S-1]←[S-1]+[S]+Carry; Carry ← 0; S ← S - 1; trap on overflow.
RADD RRR 3 Rc ← Ra + Rb + Carry; Carry ← 0; trap on overflow.
QADD QR 2 Rc ← Ra + Rb + Carry; Carry ← 0; trap on overflow.
RUADD RRR 3 Rc ← Ra + Rb + Carry; Carry ← CarryOut.
RVADD RRR 3 Rc ← Ra + Rb.
Subtraction
SUBB LB 2 [S] ← [S] - zExt[literal]- Carry; Carry ← 0; trap on overflow.
SUBDB LH 3 [S] ← [S] - zExt[literal]- Carry; Carry ← 0; trap on overflow.
SUBQB LW 5 [S] ← [S] - zExt[literal]- Carry; Carry ← 0; trap on overflow.
SUB I 1 [S-1 ] ← [S-1 ] - [S] - Carry; Carry ← 0;S←S-1;trap on overflow.
RSUB RRR 3 Rc ← Ra - Rb - Carry; Carry ← 0; trap on overflow.
QSUB QR 2 Rc ← Ra - Rb - Carry; Carry ← 0; trap on overflow.
RUSUB RRR 3 Rc ← Ra - Rb - Carry; Carry ← NOT[CarryOut].
RVSUB RRR 3 Rc ← Ra - Rb.
Logical Operations
AND I 1 [S-1] ← [S-1] and [S]; S ← S - 1.
RAND RRR 3 Rc ← Ra AND Rb
QAND QR 2 Rc ← Ra AND Rb.
OR I 1 [S-1] ← [S-1] OR [S]; S ← S - 1.
ROR RRR 3 Rc ← Ra OR Rb.
QOR QR 2 Rc ← Ra OR Rb.
RXOR RRR 3 Rc ← Ra XOR Rb.
Loads
LIB LB 2 [S+1] ← zExt[literal]; S ← S + 1.
LIDB LH 3 [S+1] ← zExt[literal]; S ← S + 1.
LIQB LW 5 [S+1] ← literal; S ← S + 1.
LRn LR 1 [S+1] ← Locals[n]; S ← S + 1; n IN[0..16).
LCm I 1 [S+1] ← Constants[m]; m IN[0..12); S ← S + 1.
LRIn XO 2 [S+1]← Mem[Locals[n]+zExt[offset]];#S←S+1;n IN[0..16).
RB LB 2 [S] ← Mem[[S] + zExt[literal]].
QRX QR 2 Rc ← Mem[Ra + Rb].
RSB LB 2 [S+1] ← Mem[[S] + zExt[literal]]; S ← S + 1.
RRX RRR 3 Rc ← Mem[Ra + Rb].
RX I 1 [S-1] ← Mem[[S-1] + [S]]; S ← S - 1.
LGF LH 3 [S+1] ← Mem[Aux[0] + zExt[literal]]; S ← S + 1.
RRI XRO 3 Locals[regA] ← Memory[Locals[regB] + zExt[offset]].
RAI XRO 3 Locals[regA] ← Mem[Aux[regB] + zExt[offset]].
LIP LB 2 [S+1] ← ProcReg[literal]; S ← S + 1.
Stores
EXDIS I 1 [S-1] ← [S]; S ← S - 1.
DUP I 1 [S+1] ← [S]; S ← S + 1.
SRn LR 1 Locals[n] ← [S]; S ← S - 1; n IN[0..16).
WB LB 2 Mem[[S] + zExt[literal]] ← [S-1]; S ← S - 2.
WSB LB 2 Mem[[S-1] + zExt[literal]] ← [S]; S ← S - 2.
PSB LB 2 Mem[[S-1] + zExt[literal]] ← [S]; S ← S - 1.
SRIn XO 2 Mem[Locals[n] + zExt[offset]] ← [S]; S ← S - 1; n IN[0..16).
SIP LB 2 ProcReg[literal] ← [S]; S ← S - 1.
WRI XRO 3 Mem[Locals[regB]+ zExt[n]] ← Locals[regA].
WAI XRO 3 Mem[Aux[regB] + zExt[n]] ← Locals[regA].
CST LB 2 [S+1]𡤌Store[ptr: [S-2]+zExt[literal], new: [S-1], old: [S]]; S ← S + 1.
Input/Output Operations
IOD LIO 3 IsRead[PCmd]=>Stack[S+1]𡤍ispatch[Address,PCmd];S←S+1;
IsWrite[PCmd]=>Dispatch[Address,Stack[S],,PCmd];S←S-1;
IODA LIO 3 IsRead[PCmd] => Stack[S] ← Dispatch[Address+Stack[S],PCmd];
IsWrite[PCmd]=>Dispatch[Address+Stack[S],Stack[S-1],PCmd];
S←S-2;
ION LIO 3 IsRead[PCmd] => Stack[S+1] ← Dispatch[Address, PCmd];
IsWrite[PCmd] => Dispatch[Address, Stack[S], PCmd];
Field Unit Operations
FSDB LH 3 FieldDescriptor ← [S] + literal; S ← S - 1.
RFU RRR 3 Rc ← FieldUnit.Operate[Ra, Rb, FieldDescriptor]
SHL LH 3 [S] ← FieldUnit.Operate[[S], 0, literal].
SHR LH 3 [S] ← FieldUnit.Operate[[S], [S], literal].
SHDL LH 3 [S-1] ← FieldUnit.Operate[[S-1], [S], literal]; S ← S - 1.
SHDR LH 3 [S-1] ← FieldUnit.Operate[[S], [S-1], literal]; S ← S - 1.
The IFU Indices - S and L
DIS I 1 S ← S - 1.
AL LB 2 L ← L + literal.
ALS LB 2 L ← S + literal.
AS LB 2 S ← S + literal.
ASL LB 2 S ← L + literal.
No Operation (NoOps)
J1-5(~4) No Operation; (~4).
Unconditional Jumps
JB LB 2 PC ← PC + sExt[literal].
JDB LH 3 PC ← PC + sExt[literal].
JQB LW 5 PC ← literal.
JSD I 1 PC ← [S]; S ← S - 1.
JSR I 1 PC ← PC + [S]; S ← S - 1.
Conditional Jumps
RJEBj RD 3 If Rs = Rb then PC ← PC + sExt[displacement].
JEBBj LBD 3 If zExt[literal]= [S] then PC ← PC + sExt[displ]; S ← S - 1.
JNEBBj LBD 3 If zExt[literal] # [S] then PC ← PC + sExt[displ]; S ← S - 1.
RJNEBj RD 3 If Rs # Rb then PC ← PC +sExt [displacement].
RJGBj RD 3 If Rs > Rb then PC ← PC + sExt[displacement].
RJGEBj RD 3 If Rs >= Rb then PC ← PC + sExt[displacement].
RJLBj RD 3 If Rs < Rb then PC ← PC + sExt[displacement].
RJLEBj RD 3 If Rs <= Rb then PC ← PC +sExt[displacement].
Bounds Checks
RBC RRR 3 If (Ra < Rb) then Rc ← Ra else trap.
BC I 1 If NOT([S-1] < [S]) then trap; S ← S - 1.
QBC QR 2 If (Ra < Rb) then Rc ← Ra else trap.
Procedure Calls and Returns
LFC LH 3 SaveState[PC,Status]; PC ← PC + sExt[literal].
DFC LW 5 SaveState[PC,Status]; PC ← literal.
SFC I 1 SaveState[PC,Status]; PC ← [S]; S ← S - 1.
KFC I 1 SaveState[PC,Status]; mode ← kernal; PC ← InstTrap[KFC].
SFCI I 1 SaveState[PC,Status]; PC ← Mem[S].
RETN I 1 ReturnState[PC, Status].
RET LB 2 S ← L + literal; ReturnState[PC, Status].
Lisp Instructions
LADD I 1 [S-1] ← [S] + [S-1]; Carry ← 0; S ← S - 1; trap on Lisp NaN.
QLADD QR 2 Rc ← Ra + Rb; Carry ← 0; trap on Lisp NaN.
RLADD RRR 3 Rc ← Ra + Rb; Carry ← 0; trap on Lisp NaN.
LSUB I 1 [S-1] ← [S-1] - [S]; Carry ← 0; S ← S - 1; trap on Lisp NaN.
QLSUB QR 2 Rc ← Ra - Rb; Carry ← 0; trap on Lisp NaN.
RLSUB RRR 3 Rc ← Ra - Rb. Carry ← 0; trap on Lisp NaN.
Dragon
Instruction Set Summary - Alphabetical by Mnemonic
Name form bytes Description
ADD I 1 [S-1]←[S-1]+[S]+Carry; Carry ← 0; S ← S - 1; trap on overflow.
ADDB LB 2 [S] ← [S] + zExt[literal] + Carry; Carry ← 0; trap on overflow.
ADDDB LDB 3 [S] ← [S] + zExt[literal] + Carry; Carry ← 0; trap on overflow.
ADDQB LW 5 [S] ← [S] + zExt[literal] + Carry; Carry ← 0; trap on overflow.
AL LB 2 L ← L + literal.
ALS LB 2 L ← S + literal.
AND I 1 [S-1] ← [S-1] and [S]; S ← S - 1.
AS LB 2 S ← S + literal.
ASL LB 2 S ← L + literal.
BC I 1 If NOT([S-1] < [S]) then trap; S ← S - 1.
CST LB 2 [S+1]𡤌Store[ptr: [S-2]+zExt[literal], new: [S-1], old: [S]]; S ← S + 1.
DFC LW 5 SaveState[PC,Status]; PC ← literal.
DIS I 1 S ← S - 1.
DUP I 1 [S+1] ← [S]; S ← S + 1.
EXDIS I 1 [S-1] ← [S]; S ← S - 1.
FSDB LH 3 FieldDescriptor ← [S] + literal; S ← S - 1.
IOD LH 3 IsRead[PCmd]=>Stack[S+1]𡤍ispatch[Address,PCmd];S←S+1;
IsWrite[PCmd]=>Dispatch[Address,Stack[S],PCmd];S←S-1;
IODA LH 3 IsRead[PCmd] => Stack[S] ← Dispatch[Address + Stack[S], PCmd];
IsWrite[PCmd]=>Dispatch[Address+Stack[S],Stack[S-1],PCmd];
S←S-2;
ION LH 3 IsRead[PCmd] => Stack[S+1] ← Dispatch[Address, PCmd];
IsWrite[PCmd]=>Dispatch[Address,Stack[S],PCmd];
J[1-5] No Operation. (~4)
JB LB 2 PC ← PC + sExt[literal].
JDB LH 3 PC ← PC + sExt[literal].
JEBBj LBD 3 zExt[literal] = [S] => PC ← PC + sExt[displ]; S ← S - 1.
JNEBBj LBD 3 zExt[literal] # [S] => PC ← PC + sExt[displ]; S ← S - 1.
JQB LW 5 PC ← literal.
JSD I 1 PC ← [S]; S ← S + 1.
JSR I 1 PC ← PC + [S]; S ← S + 1.
KFC I 1 SaveState[PC,Status]; mode ← kernal; PC ← InstTrap[KFC].
LADD I 1 [S-1] ← [S-1] + [S]; Carry ← 0; S ← S - 1; trap on Lisp NaN.
LCm I 1 [S+1] ← Constants[m]; m IN[0..12); S ← S + 1.
LFC LH 3 SaveState[PC,Status]; PC ← PC + sExt[literal].
LGF LH 3 [S+1] ← Mem[Aux[0] + zExt[literal]]; S ← S + 1.
LIB LB 2 [S+1] ← zExt[literal]; S ← S + 1.
LIDB LH 3 [S+1] ← zExt[literal]; S ← S + 1.
LIP LB 2 [S+1] ← ProcReg[literal]; S ← S + 1.
LIQB LW 5 [S+1] ← literal; S ← S + 1.
LRIn XO 2 [S+1]← Mem[Locals[n]+zExt[offset]]; S←S+1; n IN[0..16).
LRn LR 1 [S+1] ← Locals[n]; S ← S + 1; n IN[0..16).
LSUB I 1 [S-1] ← [S-1] - [S]; Carry ← 0; S ← S - 1; trap on Lisp NaN.
OR I 1 [S-1] ← [S-1] OR [S]; S ← S - 1.
PSB LB 2 Mem[[S-1] + zExt[literal]] ← [S]; S ← S - 1.
QADD QR 2 Rc ← Ra + Rb + Carry; Carry ← 0; trap on overflow.
QAND QR 2 Rc ← Ra AND Rb.
QBC QR 2 If (Ra < Rb) then Rc ← Ra else trap.
QLADD QR 2 Rc ← Ra + Rb; Carry ← 0; trap on Lisp NaN.
QLSUB QR 2 Rc ← Ra - Rb; Carry ← 0; trap on Lisp NaN.
QOR QR 2 Rc ← Ra OR Rb.
QRX QR 2 Rc ← Mem[Ra + Rb].
QSUB QR 2 Rc ← Ra - Rb - Carry; Carry ← 0; trap on overflow.
RADD RRR 3 Rc ← Ra + Rb + Carry; Carry ← 0; trap on overflow.
RAI XRO 3 Locals[regA] ← Mem[Aux[regB] + zExt[offset]].
RAND RRR 3 Rc ← Ra AND Rb.
RB LB 2 [S] ← Mem[[S] + zExt[literal]].
RBC RRR 3 If (Ra < Rb ) then Rc ← Ra else trap.
RET LB 2 S ← L + literal; ReturnState[PC, Status].
RETN I 1 ReturnState[PC, Status];
RFU RRR 3 Rc ← FieldUnit.Operate[Ra, Rb, Field].
RJEBj RD 3 If Rs = Rb then PC ← PC + sExt[displacement].
RJGBj RD 3 If Rs > Rb then PC ← PC + sExt[displacement].
RJGEBj RD 3 If Rs >= Rb then PC ← PC + sExt[displacement].
RJLBj RD 3 If Rs < Rb then PC ← PC + sExt[displacement].
RJLEBj RD 3 If Rs <= Rb then PC ← PC +sExt [displacement].
RJNEBj RD 3 If Rs # Rb then PC ← PC +sExt [displacement].
RLADD RRR 3 Rc ← Ra + Rb; Carry ← 0; trap on Lisp NaN.
RLSUB RRR 3 Rc ← Ra - Rb. Carry ← 0; trap on Lisp NaN.
ROR RRR 3 Rc ← Ra OR Rb.
RRI XRO 3 Locals[regA] ← Memory[Locals[regB] + zExt[offset]].
RRX RRR 3 Rc ← Mem[Ra + Rb].
RSB LB 2 [S+1] ← Mem[[S] + zExt[literal]]; S ← S + 1.
RSUB RRR 3 Rc ← Ra - Rb - Carry; Carry ← 0; trap on overflow.
RUADD RRR 3 Rc ← Ra + Rb + Carry; Carry ← CarryOut.
RUSUB RRR 3 Rc ← Ra - Rb - Carry; Carry ← NOT[CarryOut].
RVADD RRR 3 Rc ← Ra + Rb.
RVSUB RRR 3 Rc ← Ra - Rb.
RX I 1 [S-1] ← Mem[[S-1] + [S]]; S ← S - 1.
RXOR RRR 3 Rc ← Ra XOR Rb.
SFC I 1 SaveState[PC, Status]; PC ← [S]; S ← S - 1.
SFCI I 1 SaveState[PC, Status]; PC ← Mem[S].
SHDL LH 3 [S-1] ← FieldUnit.Operate[[S-1], [S], literal]; S ← S - 1.
SHDR LH 3 [S-1] ← FieldUnit.Operate[[S], [S-1], literal]; S ← S - 1.
SHL LH 3 [S] ← FieldUnit.Operate[[S], 0, literal].
SHR LH 3 [S] ← FieldUnit.Operate[[S], [S], literal].
SIP LB 2 ProcReg[literal] ← [S]; S ← S - 1.
SRIn XO 2 Mem[Locals[n] + zExt[offset]] ← [S];S ← S - 1; n IN[0..16).
SRn LR 1 Locals[n] ← [S]; S ← S - 1; n IN[0..16).
SUB I 1 [S-1 ] ← [S-1 ] - [S] - Carry; Carry ← 0;S←S-1;trap on overflow.
SUBB LB 2 [S] ← [S] - zExt[literal]- Carry; Carry ← 0; trap on overflow.
SUBDB LH 3 [S] ← [S] - zExt[literal]- Carry; Carry ← 0; trap on overflow.
SUBQB LW 5 [S] ← [S] - zExt[literal]- Carry; Carry ← 0; trap on overflow.
WAI XRO 3 Mem[Aux[regB] + zExt[n]] ← Locals[regA].
WB LB 2 Mem[[S] + zExt[literal]] ← [S-1]; S ← S - 2.
WRI XRO 3 Mem[Locals[regB]+ zExt[n]] ← Locals[regA].
WSB LB 2 Mem[[S-1] + zExt[literal]] ← [S]; S ← S - 2.
Dragon Instruction Set Summary - Alphabetical by Instruction Name
Name Description
Add [S-1]←[S-1]+[S]+Carry;Carry𡤀S←S-1;
trap on overflow.
Add Byte [S]←[S]+zExt[literal]+Carry;Carry𡤀trap on oflw.
Add Double Byte [S]←[S]+zExt[literal]+Carry;Carry𡤀trap on oflw.
Add Quad Byte [S]←[S]+zExt[literal]+Carry;Carry𡤀trap on oflw.
Add to L L ← L + literal.
Add to L from Stack L ← S + literal.
Add to Stack S ← S + literal
Add to Stack from L S ← L + literal
And [S-1] ← [S] and [S-1]; S ← S - 1.
Bounds Check If Not([S-1] < [S]) then trap; S ← S - 1.
Conditional Store [S+1]𡤌Store[ptr:[S-2]+zExt[literal],new:[S-1],old:[S]];
S ← S + 1.
Direct Function Call SaveState[PC,Status]; PC ← literal.
Discard S ← S - 1.
Duplicate [S+1] ← [S]; S ← S + 1.
EXchange DIScard [S-1] ← [S]; S ← S - 1.
I/O with Data from stack IsRead[PCmd]=>Stack[S+1]𡤍ispatch[Address,PCmd];
S←S+1;
IsWrite[PCmd]=>Dispatch[Address,Stack[S],,PCmd];
S←S-1;
I/O w Data & add from stack IsRead[PCmd]=>Stack[S+1]𡤍ispatch[
Address+Stack[S],PCmd];
IsWrite[PCmd]=>Dispatch[Address+Stack[S],
Stack[S-1],PCmd];S←S-2;
I/O w No stack adjust IsRead[PCmd]=>Stack[S+1]𡤍ispatch[Address,PCmd];
IsWrite[PCmd]=>Dispatch[Address,Stack[S],PCmd];
Jump Equal Byte Byte zExt[literal] = [S] => PC ← PC + sExt[displ];
S ← S - 1.
Jump Not Equal Byte Byte zExt[literal] # [S] => PC ← PC + sExt[displ];
S ← S - 1.
Jump 1 - Jump 5 (not 4) No Operation; (not 4)
Jump Stack Direct PC ← [S]; S ← S - 1.
Jump Stack Relative PC ← PC + [S]; S ← S - 1.
Jump using Double Byte offset PC ← PC + sExt[literal].
Jump to Quad Byte address PC ← literal.
Kernel Function Call SaveState[PC,Status];mode←krnl;PC←InstTrap[KFC].
Lisp ADD [S-1] ← [S-1] + [S]; Carry ← 0; S ← S - 1;
trap on Lisp NaN.
Lisp SUBtract [S-1] ← [S-1] - [S]; Carry ← 0; S ← S - 1;
trap on Lisp NaN.
Load Constant m [S+1] ← Constants[m];m IN[0..12); S ← S + 1.
Local Function Call SaveState[PC,Status]; PC ← PC + sExt[literal].
Load Global Frame [S+1] ← Mem[Aux[0] + zExt[literal]];S←S+1.
Load Immediate Byte [S+1] ← zExt[literal]; S ← S + 1.
Load Immediate Double Byte [S+1] ← zExt[literal]; S ← S + 1.
Load Immediate Quad Byte [S+1] ← literal; S ← S + 1.
Load Register Indexed n [S+1]← Mem[Locals[n]+zExt[offset]]; S←S+1;
n IN[0..16).
Load Register n [S+1] ← Locals[n]; S ← S + 1;
n IN[0..16).
OR [S-1] ← [S-1] or [S]; S ← S - 1.
Put Swapped using
Byte offset Mem[[S-1] + zExt[literal]] ← [S];S ← S - 1.
Quick Add Rc ← Ra + Rb + Carry; Carry ← 0;trap on overflow.
Quick AND Rc ← Ra and Rb.
Quick Bounds Check If (Ra < Rb) then Rc ← Ra else trap.
Quick Lisp Add Rc ← Ra + Rb; Carry ← 0; trap on Lisp NaN.
Quick Lisp SUBtract Rc ← Ra - Rb; Carry ← 0; trap on Lisp NaN.
Quick OR Rc ← Ra OR Rb.
Quick Read indeXed Rc ← Mem[Ra + Rb];trap on overflow.
Quick Subtract Rc ← Ra - Rb - Carry; Carry ← 0.
Read Aux reg Indexed Locals[regA] ← Mem[Aux[regB] + zExt[offset]].
Read indeXed [S-1] ← Mem[[S-1] + [S]]; S ← S - 1.
Read Register Indexed Locals[regA]←Memory[Locals[regB]+zExt[offset]].
Read Save using
Byte offset [S+1] ← Mem[[S] + zExt[literal]];S←S+1.
Register Subtract Rc ← Ra - Rb - Carry;Carry𡤀trap on overflow.
Read using byte offset [S] ← Mem[[S] + zExt[literal]].
Register Add Rc ← Ra + Rb + Carry; Carry ← 0;trap on overflow.
Register AND Rc ← Ra AND Rb.
Register Bounds Check If (Ra < Rb ) then Rc ← Ra else trap.
Register Field Unit Rc ← FieldUnit.Operate[Ra, Rb, Field].
Register Jump Equal Byte If Rs = Rb then PC ← PC + sExt[displacement].
Register Jump Greater Byte If Rs > Rb then PC ← PC + sExt[displacement].
Register Jump >= Byte If Rs >= Rb then PC ← PC + sExt[displacement].
Register Jump Less Byte If Rs < Rb then PC ← PC + sExt[displacement].
Register Jump <= Byte If Rs <= Rb then PC ← PC +sExt [displacement].
Register Jump # Byte If Rs # Rb then PC ← PC +sExt [displacement].
Register Lisp ADD Rc ← Ra + Rb; Carry ← 0; trap on Lisp NaN.
Register Lisp SUBtract Rc ← Ra - Rb. Carry ← 0; trap on Lisp NaN.
Register OR Rc ← Ra OR Rb.
Register Read indeXed Rc ← Mem[Ra + Rb].
Register Unsigned Add Rc ← Ra + Rb + Carry; Carry ← CarryOut.
Register Unsigned Subtract Rc ← Ra - Rb - Carry; Carry ← NOT[CarryOut].
Register Vanilla Add Rc ← Ra + Rb.
Register Vanilla Subtract Rc ← Ra - Rb.
Register XOR Rc ← Ra XOR Rb.
RETurn S ← L + literal; ReturnState[PC, Status].
RETurn No adjustment to S ReturnState[PC, Status].
Shift Double Left [S-1] ← FieldUnit.Operate[[S-1], [S], literal];
S ← S - 1.
Shift Double Right [S-1] ← FieldUnit.Operate[[S], [S-1], literal];
S ← S - 1.
Shift Left [S] ← FieldUnit.Operate[[S], 0, literal].
Shift Right [S] ← FieldUnit.Operate[[S], [S], literal].
Stack Function Call SaveState[PC,Status]; PC ← [S]; S ← S - 1.
Stack Function Call Indirect SaveState[PC,Status]; PC ← Mem[[S]].
Store to Internal
Processor register ProcReg[literal] ← [S]; S ← S - 1.
Store Register Indexed n Mem[Locals[n] + zExt[offset]] ← [S];
S ← S - 1;n IN[0..16).
Store Register n Locals[n] ← [S]; S ← S - 1; n IN[0..16).
Substract [S-1 ] ← [S-1 ] - [S] - Carry;Carry ← 0;
S←S-1;trap on overflow.
Subtract Byte [S] ← [S] - zExt[literal]- Carry; Carry ← 0;
trap on overflow.
Subtract Double Byte [S] ← [S] - zExt[literal]- Carry; Carry ← 0;
trap on overflow.
Subtract Quad Byte [S] ← [S] - zExt[literal]- Carry; Carry ← 0;
trap on overflow.
Write Aux reg Indexed Mem[Aux[regB] + zExt[n]] ← Locals[regA].
Write Register Indexed Mem[Locals[regB]+ zExt[n]] ← Locals[regA].
Write Swapped using
Byte offset Mem[[S-1] + zExt[literal]] ← [S];S ← S - 2.
Write using Byte offset Mem[[S] + zExt[literal]] ← [S-1];S ← S - 2.
Dragon
Instruction Set Summary - by Opcode
Hex Name bytes Description
10-1C LCm 1 [S+1] ← Constants[m]; m IN[0..12); S ← S + 1.
31 DFC 5 SaveState[PC,Status]; PC ← literal.
32 LIQB 5 [S+1] ← literal; S ← S + 1.
34 ADDQB 5 [S] ← [S] + zExt[literal] + Carry; Carry ← 0; trap on overflow.
35 SUBQB 5 [S] ← [S] - zExt[literal]- Carry; Carry ← 0; trap on overflow.
36 J5 5 No Operation.
37 JQB 5 PC ← literal.
40 OR 1 [S-1] ← [S-1] OR [S]; S ← S - 1.
41 AND 1 [S-1] ← [S-1] and [S]; S ← S - 1.
42 RX 1 [S-1] ← Mem[[S-1] + [S]]; S ← S - 1.
43 BC 1 If NOT([S-1] < [S]) then trap; S ← S - 1.
44 ADD 1 [S-1]←[S-1]+[S]+Carry; Carry ← 0; S ← S - 1; trap on overflow.
45 SUB 1 [S-1 ] ← [S-1 ] - [S] - Carry; Carry ← 0;S←S-1;trap on overflow.
46 LADD 1 [S-1] ← [S-1] + [S]; Carry ← 0; S ← S - 1; trap on Lisp NaN.
47 LSUB 1 [S-1] ← [S-1] - [S]; Carry ← 0; S ← S - 1; trap on Lisp NaN.
48 DUP 1 [S+1] ← [S]; S ← S + 1.
49 DIS 1 S ← S - 1.
4B EXDIS 1 [S-1] ← [S]; S ← S - 1.
4C SFC 1 SaveState[PC, Status]; PC ← [S]; S ← S - 1.
4D SFCI 1 SaveState[PC, Status]; PC ← Mem[S].
4E RETN 1 ReturnState[PC, Status];
4F JSD 1 PC ← [S]; S ← S - 1.
54 KFC 1 SaveState[PC,Status]; mode ← kernal; PC ← InstTrap[KFC].
56 J1 1 No Operation.
57 JSR 1 PC ← PC + [S]; S ← S + 1.
60-6F LRn 1 [S+1] ← Locals[n]; S ← S + 1; n IN[0..16).
70-7F SRn 1 Locals[n] ← [S]; S ← S - 1; n IN[0..16).
80 QOR 2 Rc ← Ra OR Rb.
81 QAND 2 Rc ← Ra AND Rb.
82 QRX 2 Rc ← Mem[Ra + Rb].
83 QBC 2 If (Ra < Rb ) then Rc ← Ra else trap.
84 QADD 2 Rc ← Ra + Rb + Carry; Carry ← 0; trap on overflow.
85 QSUB 2 Rc ← Ra - Rb - Carry; Carry ← 0; trap on overflow.
86 QLADD 2 Rc ← Ra + Rb; Carry ← 0; trap on Lisp NaN.
87 QLSUB 2 Rc ← Ra - Rb; Carry ← 0; trap on Lisp NaN.
88 ALS 2 L ← S + literal.
89 AL 2 L ← L + literal.
8A ASL 2 S ← L + literal.
8B AS 2 S ← S + literal.
8C CST 2 [S+1]𡤌Store[ptr: [S-2]+zExt[literal], new: [S-1], old: [S]]; S ← S + 1.
8E RET 2 S ← L + literal; ReturnState[PC, Status].
90 LIP 2 [S+1] ← ProcReg[literal]; S ← S + 1.
91 SIP 2 ProcReg[literal] ← [S]; S ← S - 1.
92 LIB 2 [S+1] ← zExt[literal]; S ← S + 1.
94 ADDB 2 [S] ← [S] + zExt[literal] + Carry; Carry ← 0; trap on overflow.
95 SUBB 2 [S] ← [S] - zExt[literal]- Carry; Carry ← 0; trap on overflow.
96 J2 2 No Operation.
97 JB 2 PC ← PC + sExt[literal].
98 RB 2 [S] ← Mem[[S] + zExt[literal]].
99 WB 2 Mem[[S] + zExt[literal]] ← [S-1]; S ← S - 2.
9A RSB 2 [S+1] ← Mem[[S] + zExt[literal]]; S ← S + 1.
9B WSB 2 Mem[[S-1] + zExt[literal]] ← [S]; S ← S - 2.
9F PSB 2 Mem[[S-1] + zExt[literal]] ← [S]; S ← S - 1.
A0-AF LRIn 2 [S+1]← Mem[Locals[n]+zExt[offset]]; S←S+1; n IN[0..16).
B0-BF SRIn 2 Mem[Locals[n] + zExt[offset]] ← [S];S ← S - 1; n IN[0..16).
C0 ROR 3 Rc ← Ra OR Rb.
C1 RAND 3 Rc ← Ra AND Rb.
C2 RRX 3 Rc ← Mem[Ra + Rb].
C3 RBC 3 If (Ra < Rb ) then Rc ← Ra else trap.
C4 RADD 3 Rc ← Ra + Rb + Carry; Carry ← 0; trap on overflow.
C5 RSUB 3 Rc ← Ra - Rb - Carry; Carry ← 0; trap on overflow.
C6 RLADD 3 Rc ← Ra + Rb; Carry ← 0; trap on Lisp NaN.
C7 RLSUB 3 Rc ← Ra - Rb. Carry ← 0; trap on Lisp NaN.
C8 RXOR 3 Rc ← Ra XOR Rb.
CA RFU 3 Rc ← FieldUnit.Operate[Ra, Rb, Field].
CC RVADD 3 Rc ← Ra + Rb.
CD RVSUB 3 Rc ← Ra - Rb.
CE RUADD 3 Rc ← Ra + Rb + Carry; Carry ← CarryOut.
CF RUSUB 3 Rc ← Ra - Rb - Carry; Carry ← NOT[CarryOut].
D0 LGF 3 [S+1] ← Mem[Aux[0] + zExt[literal]]; S ← S + 1.
D1 LFC 3 SaveState[PC,Status]; PC ← PC + sExt[literal].
D2 LIDB 3 [S+1] ← zExt[literal]; S ← S + 1.
D3 FSDB 3 FieldDescriptor ← [S] + literal; S ← S - 1.
D4 ADDDB 3 [S] ← [S] + zExt[literal] + Carry; Carry ← 0; trap on overflow.
D5 SUBDB 3 [S] ← [S] - zExt[literal]- Carry; Carry ← 0; trap on overflow.
D6 J3 3 No Operation.
D7 JDB 3 PC ← PC + sExt[literal].
D8 RAI 3 Locals[regA] ← Mem[Aux[regB] + zExt[offset]].
D9 WAI 3 Mem[Aux[regB] + zExt[n]] ← Locals[regA].
DA RRI 3 Locals[regA] ← Memory[Locals[regB] + zExt[offset]].
DB WRI 3 Mem[Locals[regB]+ zExt[n]] ← Locals[regA].
DC IODA 3 IsRead[PCmd] => Stack[S]𡤍ispatch[Address+Stack[S],PCmd];
IsWrite[PCmd]=>Dispatch[Address+Stack[S],Stack[S-1],PCmd];
S←S-2;
DD IOD 3 IsRead[PCmd]=>Stack[S+1]𡤍ispatch[Address,PCmd];S←S+1;
IsWrite[PCmd]=>Dispatch[Address,Stack[S],,PCmd];S←S-1;
DE ION 3 IsRead[PCmd] => Stack[S+1] ← Dispatch[Address, PCmd];
IsWrite[PCmd] => Dispatch[Address, Stack[S], PCmd];
E1 RJEB 3 If Rs = Rb then PC ← PC + sExt[displacement].
E2 RJLB 3 If Rs < Rb then PC ← PC + sExt[displacement].
E3 RJLEB 3 If Rs <= Rb then PC ← PC +sExt [displacement].
E5 RJNEB 3 If Rs # Rb then PC ← PC +sExt [displacement].
E6 RJGEB 3 If Rs >= Rb then PC ← PC + sExt[displacement].
E7 RJGB 3 If Rs > Rb then PC ← PC + sExt[displacement].
E9 RJNEBj 3 If Rs # Rb then PC ← PC +sExt [displacement].
EA RJGEBj 3 If Rs >= Rb then PC ← PC + sExt[displacement].
EB RJGBj 3 If Rs > Rb then PC ← PC + sExt[displacement].
ED RJEBj 3 If Rs = Rb then PC ← PC + sExt[displacement].
EE RJLBj 3 If Rs < Rb then PC ← PC + sExt[displacement].
EF RJLEBj 3 If Rs <= Rb then PC ← PC +sExt [displacement].
F0 JEBB 3 zExt[literal] = [S] => PC ← PC + sExt[displ]; S ← S - 1.
F1 JNEBB 3 zExt[literal] # [S] => PC ← PC + sExt[displ]; S ← S - 1.
F2 JEBBj 3 zExt[literal] = [S] => PC ← PC + sExt[displ]; S ← S - 1.
F3 JNEBBj 3 zExt[literal] # [S] => PC ← PC + sExt[displ]; S ← S - 1.
F8 SHL 3 [S] ← FieldUnit.Operate[[S], 0, literal].
F9 SHR 3 [S] ← FieldUnit.Operate[[S], [S], literal].
FA SHDL 3 [S-1] ← FieldUnit.Operate[[S-1], [S], literal]; S ← S - 1.
FB SHDR 3 [S-1] ← FieldUnit.Operate[[S], [S-1], literal]; S ← S - 1.
Dragon Instruction
Map
This instruction map shows the current placement of instruction codes in the opcode space. It has been arranged to minimize the decoding difficulty for the IFU.
Octal Form Len --0 --1 --2 --3 --4 --5 --6 --7
00- I 1 x000b x001b x002b x003b x004b x005b x006b x007b
01- I 1 x010b x011b x012b x013b x014b x015b x016b x017b
02- I 1 LC0 LC1 LC2 LC3 LC4 LC5 LC6 LC7
03- I 1 LC8 LC9 LC10 LC11 x034b x035b x036b x037b
04- LW 5 x040b x041b x042b x043b x044b x045b x046b x047b
05- LW 5 x050b x051b x052b x053b x054b x055b x056b x057b
06- LW 5 x060b DFC LIQB x063b ADDQB SUBQB J5 JQB
07- LW 5 x070b x071b x072b x073b x074b x075b x076b x077b
10- I 1 OR AND RX BC ADD SUB LADD LSUB
11- I 1 DUP DIS x112b EXDIS SFC SFCI RETN JSD
12- I 1 x120b x121b x122b x123b KFC x125b J1 JSR
13- I 1 x130b x131b x132b x133b x134b x135b x136b x137b
14- LR 1 LR0 LR1 LR2 LR3 LR4 LR5 LR6 LR7
15- LR 1 LR8 LR9 LR10 LR11 LR12 LR13 LR14 LR15
16- LR 1 SR0 SR1 SR2 SR3 SR4 SR5 SR6 SR7
17- LR 1 SR8 SR9 SR10 SR11 SR12 SR13 SR14 SR15
20- QR 2 QOR QAND QRX QBC QADD QSUB QLADD QLSUB
21- LB 2 ALS AL ASL AS CST x215b RET x217b
22- LB 2 LIP SIP LIB x223b ADDB SUBB J2 JB
23- LB 2 RB WB RSB WSB x234b x235b x236b PSB
24- XO 2 LRI0 LRI1 LRI2 LRI3 LRI4 LRI5 LRI6 LRI7
25- XO 2 LRI8 LRI9 LRI10 LRI11 LRI12 LRI13 LRI14 LRI15
26- XO 2 SRI0 SRI1 SRI2 SRI3 SRI4 SRI5 SRI6 SRI7
27- XO 2 SRI8 SRI9 SRI10 SRI11 SRI12 SRI13 SRI14 SRI15
30- RRR 3 ROR RAND RRX RBC RADD RSUB RLADD RLSUB
31- RRR 3 RXOR *** RFU *** RVADD RVSUB RUADD RUSUB
32- LH 3 LGF LFC LIDB FSDB ADDDB SUBDB J3 JDB
33- XRO/LIO 3 RAI WAI RRI WRI IODA IOD ION x337b
34- RD 3 *** RJEB RJLB RJLEB *** RJNEB RJGEB RJGB
35- RD 3 *** RJNEBJ RJGEBJ RJGBJ *** RJEBJ RJLBJ RJLEBJ
36- LBD 3 JEBB JNEBB JEBBJ JNEBBJ x364b x365b x366b x367b
37- LH 3 SHL SHR SHDL SHDR x374b x375b x376b x377b
*** => Undefined behavior
--- => Mixed format line
xop => Takes Xop trap
Dragon Instruction Notes
I - Implicit
LB - Literal Byte
LH - Literal Halfword
LW - Literal Word
LBD - Literal Byte Displacement
RRR - Registers to Register
QR - Quick Register
RD - Register Displacement
LR - Locals Register
XO - Index Register Offset
XRO - Index Register Register Offset
Locals[n] one of the 16 local registers
AuxRegs[n] one of the 16 auxilliary registers
Constants[m] one of the 12 constant registers
[S], [S-1] the top of stack, or just below it
[S]-, [S-1]- stack operand with S decrement (Ra & Rb only)
[S+1]+ push onto the stack (for Rc only)
Locals and AuxRegs cannot be used in the same instruction.
S is incremented by S after the instruction completes.
For a short register specification (Rs), the operand may be [S], [S] where S ← S - 1, Constants[0] or Constants[1].