Signal Naming Conventions
Most signal root names have a two or three character suffix which provides timing information. The first of these characters is a number which indicates the elapsed cycles since the instruction which generated the signal entered the pipeline. The letter(s) following this number can be any of the following: (A, B, AB, BA). The first letter indicates in what phase the signal is generated. The presence of the second letter indicates that the signal is stable throughout the next phase. The absence of the second letter indicates that the signal is undefined during the next phase.
Except where noted, signals generated in a particular phase are only expected to be stable at the end of that phase (in time to meet latch setup times of the receiving device).
Names for the individual bits of multi-bit signals and busses are derived from the root name by appending a period and zero filled octal integers. For instance, the most significant and least significant bits of the 32 bit KBus are named KBus.00 and KBus.37 respectively whereas the most significant bit of the 5 bit (1 octal digit) wide EUAluOp2AB is EUAluOp2AB.0.
Positive logic is assumed (asserted = TRUE = 1 = more positive logic voltage); negative-logic signals have an extra "N" at or very near the beginning of the signal name (e.g., DNSelectAB for DBus Negative-TRUE Select)
Signal (Root) Names
Signal Size Pins I/O Notes
MSB LSB
VDD 1 1
IPCmnd3A 4 5 2 O PBus command to IFUCache
IPFaultB 4 9 6 I PBus Fault from IFUCache
IPRejectB 1 10 I PBus Reject from IFUCache
spare 7 11 17
GND 1 18
VDD 1 19
Reset 1 20 I Reset control
Reschedule 1 21 I Reschedule control
spare 1 22
Clock 1 23 I Clock
PhaseClockSel 1 24 I Use AB clocks (debug)
ExplicitPhA 1 25 I Clock phase A (debug)
ExplicitPhB 1 26 I Clock phase B (debug)
spare 1 27
DHoldAB 1 28 I Serial Debug Hold command
DShiftAB 1 29 I Serial Debug Shift command
DExecuteAB 1 30 I Serial Debug Execute command
DNSelectAB 1 31 I Serial Debug Chip Select control
DDataInAB 1 32 I Serial Debug Data in
DDataOutAB 1 33 O Serial Debug Data out
spare 2 34 35
GND 1 36
VDD 1 37
KBus.00 - KBus.17 16 38 53 I/O Control bus between EU and IFU
GND 1 54
VDD 1 55
KBus.20 - KBus.37 16 56 71 I/O Control bus between EU and IFU
GND 1 72
VDD 1 73
FPConnected 1 74 I Floating point unit is connected
EUWriteField3BA 1 75 O Write field register control to EU
EUWriteToPBus3AB 1 76 O PBus drive control to EU
EURes3BisPBus3AB 1 77 O Mux control to EU
EUCondition2BA 1 78 I Condition test result from EU
EURes3AisCBus2BA 1 79 O Mux control to EU
EUSt3AisCBus2BA 1 80 O Mux control to EU
EUCondSel2AB 4 81 84 O Alu condition select to EU
EUAluOp2AB 5 85 89 O Alu op code to EU
EUAluLeftSrc1BA * 2 *0 *1 O Mux control to EU
EUAluRightSrc1BA * 2 *2 *3 O Mux control to EU
EUStore2ASrc1BA * 2 *4 *5 O Mux control to EU
GND 1 90
VDD 1 91
spare 7 92 98
DPRejectB 1 99 I PBus Reject from EUCache or FPU
DPFaultB 4 100 103 I PBus Fault from EUCache or FPU
DPCmnd3A 4 104 107 O PBus command to EUCaches and FPU
GND 1 108
VDD 1 109
IPData.20 - IPData.37 16 125 110 I/O PBus address to or data from IFUCache
GND 1 126
VDD 1 127
IPData.00 - IPData.17 16 143 128 I/O PBus address to or data from IFUCache
GND 1 144
* - Current plans are to multiplex these 6 signals into the 4th byte of the KBus during phase B.
(ie. *2 => KBus.32).
8 GND
8 VDD
18 spares
Signal Descriptions
IPCmnd3A **
This 4 bit control commands a IPBus operation to the IFU caches. Of the possible commands defined in Dragon.PBusCommands, only NoOp and Fetch are currently used on the IFU PBus
IPFaultB **
This 4 bit status signal is driven by the IFU caches. When non-zero, it causes a fault dependent trap to occur. Of the possible faults defined in Dragon.PBusFaults, only Page is currently valid on the IFU PBus.
IPRejectB **
This 1 bit status signal is driven by the IFU caches. When non-zero, it indicates a instruction fetch delay.
Reset
This 1 bit asynchronous control causes the IFU to clear its internal state and perform a reset trap. The line must be held valid for a minimum of 4 cycles.
(Check this, would 1 work?)
Reschedule
This 1 bit asynchronous interrupt control is shared by all IFU's and causes each to take a Reschedule trap. The effect of the control may be delayed if a multi cycle instruction is being executed or traps are disabled (controlled using an internal IFU status bit).
Clock
100 ns period with equal (50 ns) half cycles.
PhaseClockSel
To be used during chip debug, this signal disables the Clock input and causes the internal Phase A and Phase B clocks to be driven by ExplicitPhA and ExplicitPhB rather than the internal clock phase generation circuitry.
ExplicitPhA
ExplicitPhB
DHoldAB
DShiftAB
DExecuteAB
DNSelectAB
DDataInAB
DDataOutAB
KBus
This 32 bit bus provides two way communication between the IFU and EU. During phase A, it is a bidirectional data bus. During phase B, it always carries the two ALU source register addresses and the one destination register address from the IFU to the EU.
FPConnected
This 1 bit boolean is used to tell the IFU that a FPU is connected to the DPBus. This input will be tied low on first units of the Dragon processor and will cause the floating point opcodes to be executed as XOps (without hardware assist).
EUWriteField3BA
This 1 bit boolean is used to tell the EU to copy the current contents of its CBus to its local copy of the Field register (a register which controls the operation of the Field unit).
EUWriteToPBus3AB
This 1 bit boolean is active when a DPBus write operation is taking place.
EURes3BisPBus3AB
This 1 bit boolean is active when a DPBus read operation is taking place.
EUCondition2BA
When true (and both DPReject and DPFault are not active), this 1 bit boolean from the EU to the IFU will cause succeeding instructions already in the pipeline to be cleared and a trap or jump to take place.
EURes3AisCBus2BA
When true, this 1 bit boolean control causes the current value on the EU's CBus (the result of the preceding instruction) to be used as the result of the next instruction.
EUSt3AisCBus2BA
When true, this 1 bit boolean control causes the current value on the EU's CBus (the result of the preceding instruction) to be used as the value to be stored on the next instruction.
EUCondSel2AB
This 4 bit control field selects the test to be performed by the ALU and is defined in:
Dragon.CondSelects
EUAluOp2AB
This 5 bit control field selects the operation to be performed by the ALU and is defined in:
Dragon.ALUOps
EUAluLeftSrc1BA
This 2 bit control field selects the left hand operand into the EU ALU and is defined as:
Dragon.ALULeftSources = {aBus(0), rBus(1), cBus(2), reserve3(3)}
EUAluRightSrc1BA
This 2 bit control field selects the right hand operand into the EU ALU and is defined as:
Dragon.ALURightSources = {bBus(0), rBus(1), cBus(2), kBus(3)}
EUStore2ASrc1BA
This 2 bit control field selects the value used is DPBus store operations and is defined as:
Dragon.Store2ASources = {bBus(0), rBus(1), cBus(2), reserve3(3)}
DPRejectB **
This 1 bit status signal is driven by the IFU caches. When non-zero, it indicates a instruction fetch delay.
DPFaultB **
This 4 bit status signal is driven by the IFU caches. When non-zero, it causes a fault dependent trap to occur. Of the possible faults defined in Dragon.PBusFaults, only Page is currently valid on the IFU PBus.
DPCmnd3A
This 4 bit control commands a DPBus operation to either the DPBus caches or the FPU and is defined as:
Dragon.PBusCommands.
IPData **
This 32 bit PBus connects the IFU to the IFU's caches. During phase A, the IFU sends an address and during phase B the caches may respond with data.
** A more complete definition of all PBus operations can be found on:
/Indigo/Dragon/Documentation/PBus/PBusSpecs.tioga