The main function of BIC is to provide access of client circuits to the Dynabus.

Hybrid to board: BIC has 24 data channels enabled by the OR of four grant lines (Send), two Request lines and four signals which are ORed together. All these signals are latched and inverted before being put on the Dynabus. Typically, four clients can wire-OR a fraction of their Dynabus ouput signals on the data lines.

Board to hybrid: 24 data channels provide the Dynabus input data to client chips on the hybrid.

BIC also provides 3 pairs of generic inverting buffers for various DBus signals. These are not strictly necessary, but are used to guarantee that the DBus will not be arbitrarily slow. The hybrid to board lines are typically used for amplifying DBusOut and are enabled by DOEn.

A pair of delay lines controlled from DBus-loadable 4-bit registers are used to set the skew between an early clock nEarly and the local or external clock LocCKOut and ExtCKOut. This mechanism is temporary and will be replaced by VCO-based logic.

On the Dynabus side, input signals vary in the 0 to +2V range and are received through a threshold-adjustable receiver (RecAdj). Clocks are also 2V signals, and have similar receivers controlled by CKRecAdj. The proper value for these voltages is to be determined experimentally; ultimately, they will be generated internally by an appropriate pile of analog logic.

Ouput signals are pulled-down only since the Dynabus has external pull-up resistors connected to +2V. A weak pull-up can also bring (ver-r-r-y slo-o-o-owly) these lines up. These pull-ups have no role in practice; they are mostly present for testing and simulation convenience.

On the hybrid side, all signals are CMOS-level (0 to +5V).

The BIC uses two sets of power supplies: Vdd (+5V) and Gnd (0V) for the logic and the hybrid pad drivers, and Gnd2V (0V) for the Dynabus drivers. The two Gnd are not connected on the chip to prevent spikes generated when driving the Dynabus to affect the logic.

Two external analog voltages, RecAdj and CKRecAdj, control the threshold of the Dynabus receivers and clock receivers, respectively.

BIC receives seven clock-related signals used to perform several functions: run a reference clock through two DBus-controlled delay lines, provide clock to another chip on the hybrid (the client), compare its clock and the client's clock with a reference clock.

nEClock: the inverted early clock; runs through two delay lines.

LocCKOut: the output of one delay line; normally connected to ChipCKIn.

ExtCKOut: the output of the other delay line; provides clock to its client.

ChipCKIn: the high-power clock for BIC itself; amplified twice and distributed.

ChipCKOut: the result of amplifying ChipCKIn.

ExtCKIn: the clock sent back by the client, after amplification.

Clock: the reference clock, used to sample ExtCKIn and ChipCKOut.

DBusIn[0..7): the usual DBus plus HybridSel.

DBusOut: the output of the DBus scan path; tristate when unused.

DCS[0..3): DBus chip select, to address any of 3 other chips on the hybrid.

nSStop: the synchronous stop.

DOEn: enables the DBus drivers on the Dynabus side.

Name[0..3): a constant value hardwired through bonding.

BInH[0..24): generic data signals from the hybrid. Enabled by Send; latched.

RqIn[0..2): request signals from the hybrid; latched.

OrInH[0..4): ORed together; latched.

DInH[0..3): DBus signals from the hybrid.

BOutH[0..24): generic data signals to the hybrid (from nBInB); latched.

DOutH[0..24): DBus signals to the hybrid (from nDInB).

Send[0..4): the four wires are ORed, latched once, and enable the BInH inputs.

nBInB[0..24): generic data signals from the Dynabus; latched.

nDInB[0..3): DBus signals from the Dynabus.

nBOutB[0..24): generic data signals to the Dynabus (from BInH).

nOrOutB: to Dynabus (from OrInH).

nRqOutB[0..2): request signals to the Dynabus (from RqIn).

nDOutB[0..3): DBus signals to the Dynabus (from DInH).Enabled by DOEn.

An 8-bit shift register, loaded when DAddress. The 3 high-order bits CID are compared to the Name of this particular BIC. If match and ~DAddress and HybridSel then the following two bits CS are decoded into four bits. The three low-order bits DCS are used to address others circuits on the hybrid. The high order bit is used to enable a decoding of the remaining 3 low-order bits in the address register (RS). This 3-to-8 deocoder is used to address the internal scan path of the BIC according to the table:

This 16-bit shift register is loaded when DAddress is asserted. It's the scan path number 0 by DBus requirement. The value is 5081H=0101,000010,000001 where 0101 is the mandatory pattern, 2 is the type (BIC) and 1 is the version.

Most flops in the data path are connected to form a 2*(24+2)=52-bit shift register, scan path number 1. The exception is the flop preceeded by a 4-input OR, used by SStop, Shared and Owner. DShiftCK is differentiated to produce a one cycle pulse used to shift the register. The order is, starting on lsb:

Notice the existence of two extra flops which can be accessed only through shift or reset; they are present only for layout reason.

Since flops of BOutH (and the extras) are reset to 1 and flops of nBOutB and nRqOutB are reset to 0, the pattern after reset is (01)26.

The skew of the internal and external clocks can be controlled through two independent 4-bit shift registers, which can be read or written. The scan paths are 2 (read external), 3 (read internal), 4 (write external), 5 (write internal).

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