Install DAUser SCCmosB PadFrames _ CedarProcess.SetPriority[background] _ &design _ CDIO.ReadDesign["BIC.dale", NIL, NIL, NIL] _ &cx _ Sisyph.Create[&design, NIL] Date _ &ct _ Sisyph.ES["DBusControl.sch", &cx] _ CoreProperties.PutCellTypeProp[&ct, $numRows, NEW[NAT_13]] -- used 15 _ CoreProperties.PutCellTypeProp[&ct, $Investment, $veryLong] -- try hard!!! _ &ob _ PWCore.Layout[&ct] _ CoreIO.ReportSaveCellType[&ct] _ PW.Draw[&ob] Date _ &ct _ Sisyph.ES["inner.sch", &cx] _ &ob _ PWCore.Layout[&ct] _ CoreIO.ReportSaveCellType[&ct] _ PW.Draw[&ob] Date _ &ct _ Sisyph.ES["BIC.sch", &cx] _ &ob _ PWCore.Layout[&ct] _ PWCore.Store[&ct, TRUE] _ PW.Draw[&ob] Date 8LayoutBIC.cm Louis Monier February 1, 1987 8:59:18 pm PST Last Edited by: Louis Monier July 30, 1987 7:17:49 pm PDT -- SC block -- The inner -- The whole chip -- Read from file _ &ct _ CoreIO.RestoreCellType["BIC", NIL] _ &ob _ PWCore.Layout[&ct] _ PW.Draw[&ob] -- Quick version of the chip for simulation Install DAUser SCCmosB PadFrames _ CedarProcess.SetPriority[background] _ &design _ CDIO.ReadDesign["BIC.dale", NIL, NIL, NIL] _ &cx _ Sisyph.Create[&design, NIL] _ &ct _ Sisyph.ES["DBusControl.sch", &cx] _ CoreProperties.PutCellTypeProp[&ct, $numRows, NEW[NAT_13]] -- used 15 _ CoreProperties.PutCellTypeProp[&ct, $Investment, $veryLong] -- try hard!!! _ &ob _ PWCore.Layout[&ct] _ CoreIO.ReportSaveCellType[&ct] _ &ct _ Sisyph.ES["inner.sch", &cx] _ &ob _ PWCore.Layout[&ct] _ CoreIO.ReportSaveCellType[&ct] _ &ct _ Sisyph.ES["BIC.sch", &cx] _ &ob _ PWCore.Layout[&ct] _ PWCore.Store[&ct, TRUE] -- Versatec Plot CDPlot Sleepy -k BICForPlot -- Applying Static _ Static.CountLeafConnections[&ct, Static.CheckCount, CoreFlat.CreateCutSet[labels: LIST["Logic"]]] Ê ˜™Icode™,K™9—J˜J˜ J˜Jšœ&˜&Jš œÏkœœœœ˜6Jšœœ˜#J˜J˜™Jšœ)˜)Jšœ0œœÏc ˜GJšœ?ž˜MJ˜Jšœ ˜ J˜J˜—™Jšœ#˜#J˜Jšœ ˜ J˜J˜—™Jšœ!˜!J˜Jšœœ˜J˜J˜—J˜™Jšœ*™*J™J™—J™šÏb+™+J™ Jšœ&™&Jš œœœœœ™6Jšœœ™#J™Jšœ)™)Jšœ0œœž ™GJšœ?ž™MJ™Jšœ ™ J™Jšœ#™#J™Jšœ ™ J™Jšœ!™!J™Jšœœ™—J˜JšŸ™Jšœ™J™JšŸ™JšœTœ™cJ˜—…—žv