<> <> <> Install DAUser SCCmosB PadFrames _ CedarProcess.SetPriority[background] _ &design _ CDIO.ReadDesign["BIC.dale", NIL, NIL, NIL] _ &cx _ Sisyph.Create[&design, NIL] Date <<-- SC block>> _ &ct _ Sisyph.ES["DBusControl.sch", &cx] _ CoreProperties.PutCellTypeProp[&ct, $numRows, NEW[NAT_13]] -- used 15 _ CoreProperties.PutCellTypeProp[&ct, $Investment, $veryLong] -- try hard!!! _ &ob _ PWCore.Layout[&ct] _ CoreIO.ReportSaveCellType[&ct] _ PW.Draw[&ob] Date <<-- The inner>> _ &ct _ Sisyph.ES["inner.sch", &cx] _ &ob _ PWCore.Layout[&ct] _ CoreIO.ReportSaveCellType[&ct] _ PW.Draw[&ob] Date <<-- The whole chip>> _ &ct _ Sisyph.ES["BIC.sch", &cx] _ &ob _ PWCore.Layout[&ct] _ PWCore.Store[&ct, TRUE] _ PW.Draw[&ob] Date <<-- Read from file>> <<_ &ct _ CoreIO.RestoreCellType["BIC", NIL]>> <<_ &ob _ PWCore.Layout[&ct]>> <<_ PW.Draw[&ob]>> <<>> <<-- Quick version of the chip for simulation>> <> <<_ CedarProcess.SetPriority[background]>> <<_ &design _ CDIO.ReadDesign["BIC.dale", NIL, NIL, NIL]>> <<_ &cx _ Sisyph.Create[&design, NIL]>> <<>> <<_ &ct _ Sisyph.ES["DBusControl.sch", &cx]>> <<_ CoreProperties.PutCellTypeProp[&ct, $numRows, NEW[NAT_13]] -- used 15>> <<_ CoreProperties.PutCellTypeProp[&ct, $Investment, $veryLong] -- try hard!!!>> <<_ &ob _ PWCore.Layout[&ct]>> <<_ CoreIO.ReportSaveCellType[&ct]>> <<>> <<_ &ct _ Sisyph.ES["inner.sch", &cx]>> <<_ &ob _ PWCore.Layout[&ct]>> <<_ CoreIO.ReportSaveCellType[&ct]>> <<>> <<_ &ct _ Sisyph.ES["BIC.sch", &cx]>> <<_ &ob _ PWCore.Layout[&ct]>> <<_ PWCore.Store[&ct, TRUE]>> <<-- Versatec Plot>> <> <<>> <<-- Applying Static>> <<_ Static.CountLeafConnections[&ct, Static.CheckCount, CoreFlat.CreateCutSet[labels: LIST["Logic"]]]>>