LayoutBIC.cm
Louis Monier February 1, 1987 8:59:18 pm PST
Last Edited by: Louis Monier July 30, 1987 7:17:49 pm PDT
Install DAUser SCCmosB PadFrames
← CedarProcess.SetPriority[background]
← &design ← CDIO.ReadDesign["BIC.dale", NIL, NIL, NIL]
← &cx ← Sisyph.Create[&design, NIL]
Date
-- SC block
← &ct ← Sisyph.ES["DBusControl.sch", &cx]
← CoreProperties.PutCellTypeProp[&ct, $numRows, NEW[NAT�]] -- used 15
← CoreProperties.PutCellTypeProp[&ct, $Investment, $veryLong] -- try hard!!!
← &ob ← PWCore.Layout[&ct]
← CoreIO.ReportSaveCellType[&ct]
← PW.Draw[&ob]
Date
-- The inner
← &ct ← Sisyph.ES["inner.sch", &cx]
← &ob ← PWCore.Layout[&ct]
← CoreIO.ReportSaveCellType[&ct]
← PW.Draw[&ob]
Date
-- The whole chip
← &ct ← Sisyph.ES["BIC.sch", &cx]
← &ob ← PWCore.Layout[&ct]
← PWCore.Store[&ct, TRUE]
← PW.Draw[&ob]
Date
-- Read from file
← &ct ← CoreIO.RestoreCellType["BIC", NIL]
← &ob ← PWCore.Layout[&ct]
← PW.Draw[&ob]
-- Quick version of the chip for simulation
Install DAUser SCCmosB PadFrames
← CedarProcess.SetPriority[background]
← &design ← CDIO.ReadDesign["BIC.dale", NIL, NIL, NIL]
← &cx ← Sisyph.Create[&design, NIL]
← &ct ← Sisyph.ES["DBusControl.sch", &cx]
← CoreProperties.PutCellTypeProp[&ct, $numRows, NEW[NAT�]] -- used 15
← CoreProperties.PutCellTypeProp[&ct, $Investment, $veryLong] -- try hard!!!
← &ob ← PWCore.Layout[&ct]
← CoreIO.ReportSaveCellType[&ct]
← &ct ← Sisyph.ES["inner.sch", &cx]
← &ob ← PWCore.Layout[&ct]
← CoreIO.ReportSaveCellType[&ct]
← &ct ← Sisyph.ES["BIC.sch", &cx]
← &ob ← PWCore.Layout[&ct]
← PWCore.Store[&ct, TRUE]
-- Versatec Plot
CDPlot Sleepy -k BICForPlot
-- Applying Static
← Static.CountLeafConnections[&ct, Static.CheckCount, CoreFlat.CreateCutSet[labels: LIST["Logic"]]]