[Indigo]<Dragon7.0>BIC2>BicLayoutDoc.tioga!1

DRAGON DOCUMENT TITLE

DRAGON PROJECT — FOR INTERNAL XEROX USE ONLY

Layout Generation of the Interface Chip

Colors for Richard's Chip

Louis Monier

Dragon-87-xx Written April, 1987 Revised Month, Year

Abstract: This is a guide of the layout generation for the interface chip. Richard Bruce was responsible for the logical definition of the chip and its simulation.

The second and succeeding paragraphs, if any, should have the same format as the first.

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FileName: BicLayoutDoc.tioga, .interpress

XEROX Xerox Corporation
Palo Alto Research Center
3333 Coyote Hill Road
Palo Alto, California 94304

Dragon Project - For Internal Xerox Use Only

Contents

1. Basic Ideas

2. Section 2 Title

3. Section 3 Title

Appendix A. Appendix A Title

Appendix B. Appendix B Title

ChangeLog

1. Basic Ideas

The chip is entirely described by schematics, and layout is generated using the command <Extract and Layout> in the Space-O menu on the icon BIC.icon

1.1 Constraints

Chip size: must fit in the large Ibiden pga and on the hybrid.

Non-standard cells: a lot of non-standard size transistors, mostly for large drivers and flip-flops, the two delay lines for the clock, 2V receivers.

Pads positionning: the "data" pads must be on the top and bottom sides (hybrid constraint). This translates into an akward aspect ration, about 14x3mm.

1.2 Bonding

Numbers from Pentronix.

- Pad size = 4 mils

- center to center = 6 mils (any direction, so same for double row)

- pad to any metalization (for non- passivated die) or scribe line = 1.5 mils; VTI wants 23m

- pad to center of scribe line = 1.5 mils; VTI wants 107m

- scribe line width = 4 to 6 mils

- chip should be 20 mils away form the cavity on all sides, 30 mils if any down bond is needed.

1.2 Package

The pga is a two-tier package with a 17.75mm cavity. The signal bonding tabs (66 per side) are on a 250m pitch.

1.2 Hybrid

The bonding tabs will be on three staggered rows, on a pitch of 500m. The inner row is for power, so there are two signal pads every 500m.

To fit on the hybrid, the chip should be as short as possible, around 3mm. No serious constraint on length. Signal pads for the hybrid should be on one long side, and signal pads for the board should be on the other one. The clock and DBus signals are distributed on the short sides.

1.2 Probing

The main constraint resides in corners: we should leave 20 mils between pads laying on different sides.

2. Cell Libraries

Cells for slices, pads, and standard cells.

2.1 Large cells

Used to build the "full-custom" cells. Hand place and route.

Small numbers (less than 20 cells). Standard cell look. Large transistors typically n=40m, p=100m. Well and subtrate are stitched all around (guard ring) to be hard on lactch-up; this allows ordinary drivers in the chip to be able to drive pads, thus simplifying pads.

2.2 Pads

All pads are on a 160m pitch.

I/O for the Board: One pad for input and one for output; large pull down (2/2500m) and separate ground track (Gnd2V). Used on the top side of the chip.

Power on Board side: Vdd and Gnd pads for the chip. Provides power to the chip. Used on the top side of the chip.

Generic 5V pad: Input or output; the metal square with minimum zapping protection (two diodes).

Generic power pad: Used on all three other sides of the chip.

2.3 Standard cells

Simply the usual CMosB library accesssed through Logic. Only one SC block on the left side of the chip.

3. Layout assembly

Standard cells block: A single block holding the low-power logic for synchronizing the DBus, decoding the chip slecet signals for other chips on the hybrid, providing ChipID, ... The library used is the usual CMosB library accesssed through Logic. The block takes over an hour so it is checkpointed: the icon reads a file instead of extracting the schematics, and LayoutBIC.cm makes the file. Layout atom is $SC. The position of public wires in the schematics is relevant. A public wire can appear only once at the periphery of the chip (a limitation of the placer). Once created, the object is also rotated by 270 degrees.

Slices: A slice is specified by abutting the icons in the desired order. Layout atom is $AbutX. The resulting cell is combined with a "bogus" cell whose only purpose is to fix the length of the slice (currently at 1200m). Layout atom is $CR which calls the channel router. Wires drawn in the schematics at the end of the channel will appear at the same position in the layout. The result is called a slice, and if you check the object property on the icon (try L-O-Left on normalSlice.icon), you will find how the slice is rotated by 270 degrees. Typically, the hybrid (5V) side is down, and the board (2V) side is up. There are several types of slices:

normalSlice: contains the two large flip-flops with accessories, plus the last stages of clock amplifiers. There are 27 instances of this slice in the datapath, 24 data slices, two for Request, one for "Or".

ClockSlice: contains a 16-tap delay line and the first two stages of clock amplification. Two such slies in the chip.

DBusSlice: holds the three pairs of drivers for DBus signals.

KSSlice: stands for kitchen sink. Drivers for control signals (Reset, Normal, Freeze, Shift) which come form the SC block and drive all 27 data slices. The 4-input OR that computes Grant. Two NORs which combine with the NAND gate in the OR slice to compute the 4-input OR on OrInH.

ControlSlice: Three clock drivers.

Datapath: A simple $AbutX of ClockSlice, DBusSlice, an array of 3 normalSlice for handling the "request" signals, and an array of 24 normalSlice.

Inner: The Standard cell block and the Datapath are assembled by a $CR, even though no routing takes place at this point. The smallest block is extended (a feature of $CR).

Top Pads: Pairs of power P=(Vdd, Gnd) and pair of signals S=(in, out). The pattern is PS6PS6PS6PS6PS6P, or 72 pads=12.96mm.

Other pads:

Appendix A. Appendix A Title

Body

Appendix B. Appendix B Title

Body

ChangeLog

Body