BICTest.mesa
Copyright Ó 1987 by Xerox Corporation. All rights reserved.
Last Edited by: RBruce August 25, 1987 6:03:49 pm PDT
Louis Monier August 13, 1987 5:34:38 pm PDT
DIRECTORY
Core, CoreClasses, CoreCreate, ICTest, Ports, Rope, Rosemary, TestCable;
BICTest: CEDAR PROGRAM
IMPORTS CoreClasses, CoreCreate, ICTest, Ports, Rosemary, TestCable
= BEGIN OPEN CoreCreate;
bicTest: Rope.ROPE = "BIC Test";
assignments: ICTest.Assignments ← NIL;
groups: ICTest.Groups ← NIL;
Vdd, Gnd, Gnd2V, CKRecAdj, RecAdj,
nEClock, Clock, ChipCKIn, ExtCKIn,
ChipCKOut, ExtCKOut, LocCKOut,
nDInB, nBInB,
nRqOutB, nDOutB, nBOutB, nOrOutB,
DInH, BInH, RqIn, OrInH,
DOutH, BOutH,
nSStop, DOEn, Name, DBusIn, Send,
DBusOut, DCS: NAT ← LAST[NAT]; -- ports indexes
-- structure of DBusIn
nDReset: NAT = 0;
nDFreeze: NAT = 1;
DExecute: NAT = 2;
DShiftCK: NAT = 3;
nDAddress: NAT = 4;
DBusInIndex: NAT = 5;
HybridSel: NAT = 6;
Grp: PROC[
n: NAT,
nm: Rope.ROPE,
dir: ICTest.Directionality,
for: ICTest.FormatType ← DNRZ,
del: ICTest.Delay ← 0,
wid: ICTest.Width ← 100,
sam: ICTest.Sample ← 0 ]
RETURNS[group: ICTest.Group ] = {RETURN
[[number: n, name: nm, directionality: dir, format: for, delay: del, sample: sam, width: wid]]};
InitializePublic:
PROC [public: Core.Wire] = {
[Vdd, Gnd, Gnd2V, CKRecAdj, RecAdj] ←
Ports.PortIndexes[public, "Vdd", "Gnd", "Gnd2V", "CKRecAdj", "RecAdj"];
[nEClock, Clock, ChipCKIn, ExtCKIn] ←
Ports.PortIndexes[public, "nEClock", "Clock", "ChipCKIn", "ExtCKIn"];
[ChipCKOut, ExtCKOut, LocCKOut] ←
Ports.PortIndexes[public, "ChipCKOut", "ExtCKOut", "LocCKOut"];
[nDInB, nBInB] ←
Ports.PortIndexes[public, "nDInB", "nBInB"];
[nRqOutB, nDOutB, nBOutB, nOrOutB] ←
Ports.PortIndexes[public, "nRqOutB", "nDOutB", "nBOutB", "nOrOutB"];
[DInH, BInH, RqIn, OrInH] ←
Ports.PortIndexes[public, "DInH", "BInH", "RqIn", "OrInH"];
[DOutH, BOutH] ←
Ports.PortIndexes[public, "DOutH", "BOutH"];
[nSStop, DOEn, Name, DBusIn, Send] ←
Ports.PortIndexes[public, "nSStop", "DOEn", "Name", "DBusIn", "Send"];
[DBusOut, DCS] ←
Ports.PortIndexes[public, "DBusOut", "DCS"];
[] ← Rosemary.SetFixedWire[public[Vdd], H];
[] ← Rosemary.SetFixedWire[public[Gnd], L];
[] ← Rosemary.SetFixedWire[public[Gnd2V], L];
[] ← Ports.InitTesterDrive[public[CKRecAdj], drive];
[] ← Ports.InitTesterDrive[public[RecAdj], drive];
[] ← Ports.InitTesterDrive[public[nEClock], drive];
[] ← Ports.InitTesterDrive[public[Clock], drive];
[] ← Ports.InitTesterDrive[public[ChipCKIn], drive];
[] ← Ports.InitTesterDrive[public[ExtCKIn], drive];
[] ← Ports.InitTesterDrive[public[ChipCKOut], drive];
[] ← Ports.InitTesterDrive[public[ExtCKOut], drive];
[] ← Ports.InitTesterDrive[public[LocCKOut], drive];
[] ← Ports.InitPort[public[nDInB], lc];
[] ← Ports.InitTesterDrive[public[nDInB], drive];
[] ← Ports.InitPort[public[nBInB], lc];
[] ← Ports.InitTesterDrive[public[nBInB], drive];
[] ← Ports.InitPort[public[nRqOutB], lc];
[] ← Ports.InitTesterDrive[public[nRqOutB], expect];
[] ← Ports.InitPort[public[nDOutB], lc];
[] ← Ports.InitTesterDrive[public[nDOutB], expect];
[] ← Ports.InitPort[public[nBOutB], lc];
[] ← Ports.InitTesterDrive[public[nBOutB], expect];
[] ← Ports.InitPort[public[nOrOutB], b];
[] ← Ports.InitTesterDrive[public[nOrOutB], expect];
[] ← Ports.InitPort[public[DInH], lc];
[] ← Ports.InitTesterDrive[public[DInH], drive];
[] ← Ports.InitPort[public[BInH], lc];
[] ← Ports.InitTesterDrive[public[BInH], drive];
[] ← Ports.InitPort[public[RqIn], lc];
[] ← Ports.InitTesterDrive[public[RqIn], drive];
[] ← Ports.InitPort[public[OrInH], lc];
[] ← Ports.InitTesterDrive[public[OrInH], drive];
[] ← Ports.InitPort[public[DOutH], lc];
[] ← Ports.InitTesterDrive[public[DOutH], expect];
[] ← Ports.InitPort[public[BOutH], lc];
[] ← Ports.InitTesterDrive[public[BOutH], expect];
[] ← Ports.InitPort[public[nSStop], b];
[] ← Ports.InitTesterDrive[public[nSStop], drive];
[] ← Ports.InitPort[public[DOEn], b];
[] ← Ports.InitTesterDrive[public[DOEn], drive];
[] ← Ports.InitPort[public[Name], lc];
[] ← Ports.InitTesterDrive[public[Name], drive];
[] ← Ports.InitPort[public[DBusIn], bs];
[] ← Ports.InitTesterDrive[public[DBusIn], drive];
[] ← Ports.InitPort[public[Send], bs];
[] ← Ports.InitTesterDrive[public[Send], drive];
[] ← Ports.InitPort[public[DBusOut], b];
[] ← Ports.InitTesterDrive[public[DBusOut], expect];
[] ← Ports.InitPort[public[DCS], lc];
[] ← Ports.InitTesterDrive[public[DCS], expect];
};
CreateBIC:
PUBLIC
PROC
RETURNS [ct: Core.CellType] = {
-- this public conforms to BICForSim.icon in BIC.dale
public: Wire ← WireList[
LIST[
-- power
"Vdd", "Gnd", "Gnd2V", "CKRecAdj", "RecAdj",
-- clocks
"nEClock", "Clock", "ChipCKIn", "ExtCKIn",
"ChipCKOut", "ExtCKOut", "LocCKOut",
-- board side
Seq["nDInB", 3], Seq["nBInB", 24],
Seq["nRqOutB", 2], Seq["nDOutB", 3], Seq["nBOutB", 24], "nOrOutB",
-- hybrid side
Seq["DInH", 3], Seq["BInH", 24], Seq["RqIn", 2], Seq["OrInH", 4],
Seq["DOutH", 3], Seq["BOutH", 24],
-- DBus et al.
"nSStop", "DOEn", Seq["Name", 3], Seq["DBusIn", 7], Seq["Send", 4],
"DBusOut", Seq["DCS", 3]
]];
ct ← CoreClasses.CreateUnspecified[public, "BIC"];
};
TestChip: PROC = {
R: PROC [a: ICTest.Assignment] = {assignments←CONS[a, assignments]};
ct: CellType ← CreateBIC[];
nBI: NAT ← 1; -- nBInB
BI: NAT ← 2; -- BInH
in0: NAT ← 3; -- nDInB, Send, DBusIn, Name, OrInH, RqIn, DInH, nSStop, DOEn
nBO: NAT ← 4; -- nBOutB
BO: NAT ← 5; -- BOutH
nDO: NAT ← 6; -- nDOutB
DCS: NAT ← 7; -- DCS
DBO: NAT ← 8; -- DBusOut
nROO: NAT ← 9; -- nOrOutB, nRqOutB
DOut: NAT ← 10; -- DOutH
ckI: NAT ← 11; -- nEClock, ExtCKIn, ChipCKIn
ckO: NAT ← 12; -- LocCKOut, ChipCKOut, ExtCKOut
ckRI: NAT ← 13; -- Clock
period: NAT ← 10000; -- 1000;
InitializePublic[ct.public];
groups ←
LIST[
Grp[n: nBI, nm:"nBIn", dir: force, for: NRZ], -- 2V drive
Grp[n: BI, nm:"BIn", dir: force, for: NRZ], -- 5V drive
Grp[n: in0, nm:"Inputs0", dir: force, for: NRZ], -- 5V drive
Grp[n: nBO, nm:"nBOut", dir: acquire, sam: 3*period/4], -- 2V pull-up
Grp[n: BO, nm:"BOut", dir: acquire, sam: 3*period/4], -- 5V acquire
Grp[n: nDO, nm:"nDOutB", dir: acquire, sam: 3*period/4], -- 5V acquire
Grp[n: DCS, nm:"DCS", dir: acquire, sam: 3*period/4], -- 5V acquire
Grp[n: DBO, nm:"DBusOut", dir: acquire, sam: 3*period/4], -- 5V acquire
Grp[n: nROO, nm:"nRqOutB", dir: acquire, sam: 3*period/4], -- 5V acquire
Grp[n: DOut, nm:"DOutH", dir: acquire, sam: 3*period/4], -- 5V acquire
Grp[n: ckI, nm:"ClockIn", dir: force, for: RZ, del: period/2, wid: period/3],
Grp[n: ckRI, nm:"ClockRefIn", dir: force, for: RC, del: period/3, wid: period/3],
Grp[n: ckO, nm:"ClockOut", dir: acquire, sam: 3*period/4] ];
Left: (acquire)
Location Board Byte A ByteB
AB 0 nBO[0..8) nBO[8..16)
CD 1 nBO[16..24) BO[0..8)
EF 2 BO[8..16) BO[16..24)
GH 3 nDO DCS
IJ 4 DBO nROO
KL 5 DOut ckO
Right: (drive)
Location Board Byte A ByteB
AB 0 nBI[0..8) nBI[8..16)
CD 1 nBI[16..24) BI[0..8)
EF 2 BI[8..16) BI[16..24)
GH 3 in0 in0
IJ 4 in0 in0
KL 5 ckI ckRI
L
o
a T
d e
s
B t D
o e U
a P r T
r o C D
d d h H H U
G B a e e T
r o S P B n a a
o a i a y n d d P
u r d i t e e e i
Signal Name p d e r e l r r n
----------------------------------------------------
R[["nBInB[0]", 1, 0,R,AB, A,0, 25,111,199]];
R[["nBInB[1]", 1, 0,R,AB, A,1, 26, 92,197]];
R[["nBInB[2]", 1, 0,R,AB, A,2, 27, 94,195]];
R[["nBInB[3]", 1, 0,R,AB, A,3, 28, 90,193]];
R[["nBInB[4]", 1, 0,R,AB, A,4, 29, 82,191]];
R[["nBInB[5]", 1, 0,R,AB, A,5, 30, 84,189]];
R[["nBInB[6]", 1, 0,R,AB, A,6, 31, 43,185]];
R[["nBInB[7]", 1, 0,R,AB, A,7, 32, 41,183]];
R[["nBInB[8]", 1, 0,R,AB, B,0, 17, 40,181]];
R[["nBInB[9]", 1, 0,R,AB, B,1, 18,146,179]];
R[["nBInB[10]", 1, 0,R,AB, B,2, 19,148,177]];
R[["nBInB[11]", 1, 0,R,AB, B,3, 20,154,175]];
R[["nBInB[12]", 1, 0,R,AB, B,4, 21,158,171]];
R[["nBInB[13]", 1, 0,R,AB, B,5, 22,160,169]];
R[["nBInB[14]", 1, 0,R,AB, B,6, 23, 58,167]];
R[["nBInB[15]", 1, 0,R,AB, B,7, 24, 33,165]];
R[["nBInB[16]", 1, 1,R,CD, A,0, 41, 63,163]];
R[["nBInB[17]", 1, 1,R,CD, A,1, 42, 62,161]];
R[["nBInB[18]", 1, 1,R,CD, A,2, 43,184,157]];
R[["nBInB[19]", 1, 1,R,CD, A,3, 44,186,155]];
R[["nBInB[20]", 1, 1,R,CD, A,4, 45,188,153]];
R[["nBInB[21]", 1, 1,R,CD, A,5, 46,190,151]];
R[["nBInB[22]", 1, 1,R,CD, A,6, 47,192,149]];
R[["nBInB[23]", 1, 1,R,CD, A,7, 48, 80,147]];
R[["BInH[0]", 2, 1,R,CD, B,0, 33,208, 43]]; -- was 239, 42
R[["BInH[1]", 2, 1,R,CD, B,1, 34,237, 45]]; -- was 238, 44
R[["BInH[2]", 2, 1,R,CD, B,2, 35,235, 47]]; -- was 236, 46
R[["BInH[3]", 2, 1,R,CD, B,3, 36,233, 49]]; -- was 234, 48
R[["BInH[4]", 2, 1,R,CD, B,4, 37,231, 51]]; -- was 232, 50
R[["BInH[5]", 2, 1,R,CD, B,5, 38,229, 53]]; -- was 230, 52
R[["BInH[6]", 2, 1,R,CD, B,6, 39,245, 57]]; -- was 246, 56
R[["BInH[7]", 2, 1,R,CD, B,7, 40,242, 59]]; -- was 243, 58
R[["BInH[8]", 2, 2,R,EF, A,0, 57,99, 61]]; -- was 241, 60
R[["BInH[9]", 2, 2,R,EF, A,1, 58, 129, 63]]; -- was 73, 62
R[["BInH[10]", 2, 2,R,EF, A,2, 59, 71, 65]]; -- was 72, 64
R[["BInH[11]", 2, 2,R,EF, A,3, 60, 69, 67]]; -- was 70, 66
R[["BInH[12]", 2, 2,R,EF, A,4, 61,149, 71]]; -- was 150, 70
R[["BInH[13]", 2, 2,R,EF, A,5, 62,255, 73]]; -- was 256, 72
R[["BInH[14]", 2, 2,R,EF, A,6, 63,253, 75]]; -- was 254, 74
R[["BInH[15]", 2, 2,R,EF, A,7, 64,251, 77]]; -- was 252, 76
R[["BInH[16]", 2, 2,R,EF, B,0, 56,249, 79]]; -- was 250, 78
R[["BInH[17]", 2, 2,R,EF, B,1, 55,118, 81]]; -- was 248, 80
R[["BInH[18]", 2, 2,R,EF, B,2, 54, 68, 85]]; -- was 115, 84
R[["BInH[19]", 2, 2,R,EF, B,3, 53, 66, 87]]; -- was 67, 86
R[["BInH[20]", 2, 2,R,EF, B,4, 52, 96, 89]]; -- was 65, 88
R[["BInH[21]", 2, 2,R,EF, B,5, 51, 51, 91]]; -- was 112, 90
R[["BInH[22]", 2, 2,R,EF, B,6, 50, 49, 93]]; -- was 50, 92
R[["BInH[23]", 2, 2,R,EF, B,7, 49, 39, 95]]; -- was 59, 94
R[["nDInB[0]", 3, 3,R,GH, A,0,185,134,213]];
R[["nDInB[1]", 3, 3,R,GH, A,1,186,136,211]];
R[["nDInB[2]", 3, 3,R,GH, A,2,187, 98,209]];
R[["Send[0]", 3, 3,R,GH, A,3,188,164,117]];
R[["Send[1]", 3, 3,R,GH, A,4,189, 26,116]];
R[["Send[2]", 3, 3,R,GH, A,5,190, 25,115]];
R[["Send[3]", 3, 3,R,GH, A,6,191, 27,114]];
R[["DBusIn[0]", 3, 3,R,GH, A,7,192,102,239]];
R[["DBusIn[1]", 3, 3,R,GH, B,0,177,101,240]];
R[["DBusIn[2]", 3, 3,R,GH, B,1,178,207, 1]];
R[["DBusIn[3]", 3, 3,R,GH, B,2,179,206, 2]];
R[["DBusIn[4]", 3, 3,R,GH, B,3,180,205, 3]];
R[["DBusIn[5]", 3, 3,R,GH, B,4,181,204, 4]];
R[["DBusIn[6]", 3, 3,R,GH, B,5,182,203, 5]];
R[["Name[0]", 3, 3,R,GH, B,6,183, 46,207]];
R[["Name[1]", 3, 3,R,GH, B,7,184, 21,205]];
R[["Name[2]", 3, 4,R,IJ, A,0,201, 19,203]];
R[["OrInH[0]", 3, 4,R,IJ, A,1,202,211, 36]];
R[["OrInH[1]", 3, 4,R,IJ, A,2,203,226, 37]];
R[["OrInH[2]", 3, 4,R,IJ, A,3,204,210, 38]];
R[["OrInH[3]", 3, 4,R,IJ, A,4,205,225, 39]];
R[["RqIn[0]", 3, 4,R,IJ, A,5,206,212, 34]];
R[["RqIn[1]", 3, 4,R,IJ, A,6,207,122, 35]];
R[["DInH[0]", 3, 4,R,IJ, A,7,208,217, 28]]; -- was 216, 29
R[["DInH[1]", 3, 4,R,IJ, B,0,217,215, 30]]; -- was 214, 31
R[["DInH[2]", 3, 4,R,IJ, B,1,218,228, 32]]; -- was 227, 33
R[["nSStop", 3, 4,R,IJ, B,2,219,141,124]];
R[["DOEn", 3, 4,R,IJ, B,3,220,142,123]];
R[["Clock", 13, 5,R,KL, B,0,109,103,238]]; --was KLA0
R[["nEClock", 11, 5,R,KL, A,1,194,105,236]];
R[["ExtCKIn", 11, 5,R,KL, A,2,195,163,118]]; --Was now a sig?
R[["ChipCKIn", 11, 5,R,KL, A,3,196,161,120]];
R[["nBOutB[0]", 4, 0,L,AB, A,0,153,110,200]];
R[["nBOutB[1]", 4, 0,L,AB, A,1,154, 91,198]];
R[["nBOutB[2]", 4, 0,L,AB, A,2,155, 93,196]];
R[["nBOutB[3]", 4, 0,L,AB, A,3,156, 95,194]];
R[["nBOutB[4]", 4, 0,L,AB, A,4,157, 81,192]];
R[["nBOutB[5]", 4, 0,L,AB, A,5,158, 83,190]];
R[["nBOutB[6]", 4, 0,L,AB, A,6,159, 42,186]];
R[["nBOutB[7]", 4, 0,L,AB, A,7,160, 44,184]];
R[["nBOutB[8]", 4, 0,L,AB, B,0,145, 35,182]];
R[["nBOutB[9]", 4, 0,L,AB, B,1,146,145,180]];
R[["nBOutB[10]", 4, 0,L,AB, B,2,147,147,178]];
R[["nBOutB[11]", 4, 0,L,AB, B,3,148,153,176]];
R[["nBOutB[12]", 4, 0,L,AB, B,4,149,157,172]];
R[["nBOutB[13]", 4, 0,L,AB, B,5,150,159,170]];
R[["nBOutB[14]", 4, 0,L,AB, B,6,151,121,168]];
R[["nBOutB[15]", 4, 0,L,AB, B,7,152, 64,166]];
R[["nBOutB[16]", 4, 1,L,CD, A,0,169, 34,164]];
R[["nBOutB[17]", 4, 1,L,CD, A,1,170, 57,162]];
R[["nBOutB[18]", 4, 1,L,CD, A,2,171,183,158]];
R[["nBOutB[19]", 4, 1,L,CD, A,3,172,185,156]];
R[["nBOutB[20]", 4, 1,L,CD, A,4,173,187,154]];
R[["nBOutB[21]", 4, 1,L,CD, A,5,174,189,152]];
R[["nBOutB[22]", 4, 1,L,CD, A,6,175,191,150]];
R[["nBOutB[23]", 4, 1,L,CD, A,7,176,114,148]];
R[["BOutH[0]", 5, 1,L,CD, B,0,161,239, 42]]; -- was 208, 43
R[["BOutH[1]", 5, 1,L,CD, B,1,162,238, 44]]; -- was 237, 45
R[["BOutH[2]", 5, 1,L,CD, B,2,163,236, 46]]; -- was 235, 47
R[["BOutH[3]", 5, 1,L,CD, B,3,164,234, 48]]; -- was 233, 49
R[["BOutH[4]", 5, 1,L,CD, B,4,165,232, 50]]; -- was 231, 51
R[["BOutH[5]", 5, 1,L,CD, B,5,166,230, 52]]; -- was 229, 53
R[["BOutH[6]", 5, 1,L,CD, B,6,167,246, 56]]; -- was 245, 57
R[["BOutH[7]", 5, 1,L,CD, B,7,168,243, 58]]; -- was 242, 59
R[["BOutH[8]", 5, 2,L,EF, A,0,129, 241, 60]]; -- was 99, 61
R[["BOutH[9]", 5, 2,L,EF, A,1,130, 73, 62]]; -- was 129, 63
R[["BOutH[10]", 5, 2,L,EF, A,2,131, 72, 64]]; -- was 71, 65
R[["BOutH[11]", 5, 2,L,EF, A,3,132, 70, 66]]; -- was 69, 67
R[["BOutH[12]", 5, 2,L,EF, A,4,133,150, 70]]; -- was 149, 71
R[["BOutH[13]", 5, 2,L,EF, A,5,134,256, 72]]; -- was 255, 73
R[["BOutH[14]", 5, 2,L,EF, A,6,135,254, 74]]; -- was 253, 75
R[["BOutH[15]", 5, 2,L,EF, A,7,136,252, 76]]; -- was 251, 77
R[["BOutH[16]", 5, 2,L,EF, B,0,137,250, 78]]; -- was 249, 79
R[["BOutH[17]", 5, 2,L,EF, B,1,138,248, 80]]; -- was 118, 81
R[["BOutH[18]", 5, 2,L,EF, B,2,139, 115, 84]]; -- was 68, 85
R[["BOutH[19]", 5, 2,L,EF, B,3,140, 67, 86]]; -- was 66, 87
R[["BOutH[20]", 5, 2,L,EF, B,4,141, 65, 88]]; -- was 96, 89
R[["BOutH[21]", 5, 2,L,EF, B,5,142,112, 90]]; -- was 51, 91
R[["BOutH[22]", 5, 2,L,EF, B,6,143, 50, 92]]; -- was 49, 93
R[["BOutH[23]", 5, 2,L,EF, B,7,144, 59, 94]]; -- was 39, 95
R[["nDOutB[0]", 6, 3,L,GH, A,0, 97,133,214]];
R[["nDOutB[1]", 6, 3,L,GH, A,1, 98,135,212]];
R[["nDOutB[2]", 6, 3,L,GH, A,2, 99, 97,210]];
R[["DCS[0]", 7, 3,L,GH, B,0,105,202, 6]];
R[["DCS[1]", 7, 3,L,GH, B,1,106,201, 7]];
R[["DCS[2]", 7, 3,L,GH, B,2,107,200, 8]];
R[["DBusOut", 8, 4,L,IJ, A,0, 89,108,235]];
R[["nOrOutB", 9, 4,L,IJ, B,0, 73,100,208]];
R[["nRqOutB[0]", 9, 4,L,IJ, B,1, 74, 20,206]];
R[["nRqOutB[1]", 9, 4,L,IJ, B,2, 75, 22,204]];
R[["DOutH[0]", 10, 5,L,KL, A,0, 81,216, 29]]; -- was 217, 28
R[["DOutH[1]", 10, 5,L,KL, A,1, 82,214, 31]]; -- was 215, 30
R[["DOutH[2]", 10, 5,L,KL, A,2, 83,227, 33]]; -- was 228, 32
R[["LocCKOut", 12, 5,L,KL, B,0, 65,143,122]];
R[["ChipCKOut", 12, 5,L,KL, B,1, 66, 60,113]];
R[["ExtCKOut", 12, 5,L,KL, B,2, 67,144,121]];
R[["RecAdj", 0, 0,R,AB, A,0, 25,162,119]];
R[["CKRecAdj", 0, 0,R,AB, A,0, 25,104,237]];
R[["Vdd", 0, 0,R,AB, A,0, 25, 56,144]];
R[["Vdd", 0, 0,R,AB, A,0, 25, 54,146]];
R[["Vdd", 0, 0,R,AB, A,0, 25,181,160]];
R[["Vdd", 0, 0,R,AB, A,0, 25,155,174]];
R[["Vdd", 0, 0,R,AB, A,0, 25, 85,188]];
R[["Vdd", 0, 0,R,AB, A,0, 25, 45,202]];
R[["Vdd", 0, 0,R,AB, A,0, 25,131,216]];
R[["Vdd", 0, 0,R,AB, A,0, 25,120,218]];
R[["Vdd", 0, 0,R,AB, A,0, 25, 48, 99]];
R[["Vdd", 0, 0,R,AB, A,0, 25, 37, 97]];
R[["Vdd", 0, 0,R,AB, A,0, 25,116, 83]];
R[["Vdd", 0, 0,R,AB, A,0, 25,151, 69]];
R[["Vdd", 0, 0,R,AB, A,0, 25,244, 55]];
R[["Vdd", 0, 0,R,AB, A,0, 25,240, 41]];
R[["Vdd", 0, 0,R,AB, A,0, 25,218, 27]];
R[["Vdd", 0, 0,R,AB, A,0, 25,220, 25]];
R[["Gnd", 0, 0,R,AB, A,0, 25, 53,143]];
R[["Gnd", 0, 0,R,AB, A,0, 25, 55,145]];
R[["Gnd", 0, 0,R,AB, A,0, 25,182,159]];
R[["Gnd", 0, 0,R,AB, A,0, 25,156,173]];
R[["Gnd", 0, 0,R,AB, A,0, 25, 36,187]];
R[["Gnd", 0, 0,R,AB, A,0, 25, 18,201]];
R[["Gnd", 0, 0,R,AB, A,0, 25,132,215]];
R[["Gnd", 0, 0,R,AB, A,0, 25,130,217]];
R[["Gnd", 0, 0,R,AB, A,0, 25, 17, 98]];
R[["Gnd", 0, 0,R,AB, A,0, 25, 38, 96]];
R[["Gnd", 0, 0,R,AB, A,0, 25,117, 82]];
R[["Gnd", 0, 0,R,AB, A,0, 25,152, 68]];
R[["Gnd", 0, 0,R,AB, A,0, 25,247, 54]];
R[["Gnd", 0, 0,R,AB, A,0, 25,209, 40]];
R[["Gnd", 0, 0,R,AB, A,0, 25,219, 26]];
R[["Gnd", 0, 0,R,AB, A,0, 25,221, 24]];
TestCable.Init[groups, assignments, "ChipCKIn"];
ICTest.MakeStandardViewer[
testName: bicTest,
cellType: ct,
clockAName: "ChipCKIn",
groups: groups,
assignments: assignments,
period: period ];
ICTest.RegisterTestProc[bicTest, "TestCable", TestCable.TestCable];
};
END.