<> <> <> 17/10/87 Regenerated BIC2. All tests passed: DRC, GlobalTest at transistor-level, Static and both connectivity checkers. Generated the Mebes in 2:16:42 seconds. 16/10/87 Found a bug in the router. Transistor-level simulation completed: 1190 evals in 22 minutes. 13/10/87 Things are better. Stats: 3007 nodes, 3313 nE transistors, 3253 pE transistors, 6566 transistors; total capacitance: 2028pF. scale New and improved stats: Read design in: 00:25 seconds Extraction: 06:33 seconds Layout: 44:47 seconds Save files: 03:14 seconds Lichen: 1:01:04 seconds -- 0.8 transistor ratio MintCheck: 01:18 seconds -- no problem 9/10/87 Time to get ready for the run. After talking to EMM, Richard, Pradeep and JMF, the best fix is no fix: the nDReset should be tied to Vdd so that none of the flops is reset. Same with nDFreeze then. What about accessing serially the Datapath? Nobody has an opinion. What a mess! 8/12/87 Routing and Lichen go through without a glitch. New and improved stats: Read design in: 00:25 seconds Extraction: 05:12 seconds Layout: 39:48 seconds Save files: 03:19 seconds Lichen: xx:xx seconds 8/7/87 Made the top schematics more explicit: pads positions are non-ambiguous now. General clean-up. Added the space after the delay line which caused a DRC violation. 8/5/87 Fixed the eval proc so that the "OR" flop has the same behavior on reset and normal. To be implemented and tested. 8/3/87 System simulation showed the first system bug: SStop is latched in BIC and during reset is set to 0, even though it must still be asserted and seen by the arbiters. A fix is to reset this slice (the OR) to a different value, or not to reset it at all. 8/2/87 Changed decoder of delay lines: 2 to 4 on high-order bits and 4 to 16 on low. This will make the delay between all 16 taps the same. 7/30/87 Mint timing on BIC: worst path is 25.2ns in DBus stuff: Name to comparator to decoder ... 7/29/87 Tested Data in the system simulation. Put the flop in layout. 7/28/87 Put BIC top-level in the system simulation. Tested DBus. 7/27/87 Fixed the top schematics to satisfy new rules on pins for atomic wires. The new syntax simulates again. Ready for conversion to BIC2. Converted: flop on grant, chipID=5082H, DBusOut tristate, DAddress instead of nDAddress, DSerialIn instead of DBusIn, removed a few inverters in SC block. 7/25/87 Adapted BIC, BICSim and BICTopLevel to the new Rosemary syntax 7/24/87 Created BIC2.df; Richard Bruce has the lock on BIC.df Everything below this line is the log of the first version of BIC 4/22: Added two spare pads and a lot of power pads. Complete routing with NewCabbage. Passed MintCheck and Static. Passed Lichen on all cells: pb with DBusSlice and normalSlice pb as expected with chargePump (series transistors) 4/23: Added two spare pads Generation failed in PWPins with a pin of size 0 => Rewrote the obstacle avoidance part of NewCabbage with Brian => finally generate the complete layout BICLayout.dale Plot BIC.dale and BICLayout.dale Fixed LogicRosemaryImpl to be able to simulate at transistor level Passed MintCheck on BIC.icon: no problem. 5980 fat transistors, 2964 nodes. 4/24: Routing bugs and missing pins in pads => new generation. Fixed a few cells (Genista) and modified (Bill G. request) Simulation failed very mysteriously (Rosemary bug, or stale VM?) 4/25: Raw extract and Static => OK. Simulation: infinite loop in a SC ff ??? 4/26: Fixed pads for RawExtract (overglass pins). Modified a few cells (Bill. G.) Made a cm file to Lichen all library cells; all cells for slices are OK. 4/27: Router could not route DBusOut: exchanged it with spareLeft, and it works. Created resistances for mimicking pull-ups on bus. Rosemary sim at transistor level could not handle the edge-triggered oracle and circuit: the fix is to have two clocks, the oracle clock been 1/2 phase early from the circuit clock. DRC of cells now OK. Simulation found the following bugs: the four wires of dpControl in DBusControl were inverted => now uses nQ instead of Q in normalSlice, last driver on hybrid side (n=640) was missing => added the inv640 path from OrInH to nOrOutB was computing a NOR instead of an OR => added a Nand Started writing BICSimImpl.mesa, a behavioral proc for BIC. Completed the oracle file. Executed 300 cycles, then crashed while shifting. Started a new layout. 4/28: Found out from Mike Ov. and Bill G. that we might not get the 300 PGA. Will try to squeeze the chip to fit in a 14mm cavity. Designed the last cells for the test chip. 4/29: Lost my disk. Fixed the few bugs found by Richard. Decided not to touch the pad frame. 4/30: Fixed more glitches. New layout generation completed successfuly. The truth could be BIC.core!5 666444 30-Apr-87 20:33:29 PDT BICLayout.dale!4 371088 30-Apr-87 20:35:48 PDT 5/1: Mark found geometry on 1/4 and 1/8 micron. Culprit was the power rail whose size must be an odd number. Redid layout. Problem again: the piece of code in NewCabbage that "avoids obstacles" can dump wires on a 1/8 micron grid. Mark hacked the CIF gen to accept that. After the fact: Mark and Richard finished the DRC and patched by hand a few glitches. Bugs: missing flip-flop for grant; was never in the specs (found by Louis). driver for DBousOut should be tristate; was never in the specs (found by Bill). driver for grant is too small (found by Bill). IO pairs of pads on hybrid sides were reversed (found by Louis). 6/15 to 8/17: Prepared the test for BIC. Wrote the first top-level proc. 8/25: Oracle not quite fixed by Richard. Transistor level runs 398 cycles, the top-level 314. First test of BIC works after a week of fighting the testing equipment: we can set the DBus to normal, and pass data both ways. 8/26: Tested a lot out of BIC, and it works. Set the address register, shift out ChipId, test nSStop. Fixed the top-level proc: decoders were backwards. 8/28: Made CounDown.cm, with BIC as example Extraction time: 7:39 seconds Static: 10 seconds Preparing tester: 3:08 seconds Simulation at transistor level: 252 eval/min, at 4 eval/cycle From MintCheck: Total number of nodes: 2991 Total number of transistors: 6176 total capacitance : 2044.903 pF 9/2: Wrote more test code Attempted to fix the simulation problem with DShiftCK: ran up to cycle 438. 9/3: Talked with JMF and EMM: specs on DBus were bogus 9/4: Wrote a lot more test code Tested the clock skew control: 1.1ns per tap, with a gap every four steps Zapped pads with Ed Richley: great success 9/7: Organize BICDoc.tioga 9/10..14: Organize the testprocs to work for both Rosemary and IMSTester. Lots of glitches. 9/15: Rebuild BIC with the new router and new PWCore. Try Countdown.cm: Read design: 00:00:28 seconds Extract BIC.sch: 00:06:25 seconds Run Static: 00:00:13 seconds Run MintCheck: 00:01:10 seconds Layout: 00:47:55 seconds Store Core file: 00:03:15 seconds CheckConnectivity: 00:26:56 seconds Lichen broke. Mike and Bertrand hot on the trail. 9/16: More test code. Top-level runs the same procs as the transistor-level. 9/17: Final test code. New probe station. BIC.df now verifies. 9/18: Fixed the shift DP in top level proc. Both transistor-level and top-level have passed: MinTest, BtoHTest, HtoBTest, StopTest, ShiftChipIDTest, NameandDCSTest, ClockTest, ShiftInDP, SendandDOEnTest and DBusTest. Transistor-level: initialization in 4 sec, then run at 2 sec per CK cycle (2 evals). Top-level: initialization in no time, then run at 0.16 sec per CK cycle (2 evals). 9/21: The silicon now run the same tests as above! TO DO <> <> <> <> read DBus doc and track any change (check sex of DBus signals) load ChipID on (OR DAddress DExecute) document order of pads on hybrid side but keep them document SStop??? use DBus icons? DBusConstant.icon for clock reg, DBusIn.icon, and part of DBusInterface.icon try $Stack for slices and SC block ? Logo Notes: Chip definition: need at least a month when design is frozen; less => no time to do checks Logic def Simulation: being exhaustive is almost free => test coverage use non-symetric patterns include transistor-level with no dynamic nodes Layout: Minimize at all cost the number of leave cells For every block, have systematical layout rules => no overlap, no DRC bugs when assembling Raw extraction, Static, Mintcheck, simulation DRC: on leaf cells as you go Errors are simple: missing inverters, permute xor and xnor, a and aBar, ... The best is the enemy of the good.