-- MemoryController.df -- Copyright (C) 1986 by Xerox Corporation. All rights reserved. -- Last Edited by: Gasbarro June 8, 1987 1:33:33 pm PDT -- Last Edited by: McCreight June 8, 1987 2:01:12 pm PDT -- Barth, October 15, 1986 2:28:20 pm PDT -- McCreight, June 8, 1987 11:30:56 am PDT -- contains layout and simulation for the Dragon memory controller chip Exports [Indigo]<Dragon>Top> MemoryController.df 08-Jun-87 17:37:30 PDT Exports [Indigo]<Dragon>MemoryController> +DRam.bcd!9 13-May-87 09:14:03 PDT DRam.mesa!5 05-May-87 12:54:52 PDT +DRamImpl.bcd!23 08-Jun-87 08:00:39 PDT +TestMC.bcd!56 08-Jun-87 17:36:44 PDT +TestECC.bcd!14 08-Jun-87 08:01:18 PDT +CommandDecodeFSM.bcd!23 08-Jun-87 08:00:58 PDT +ReplyControlFSM.bcd!22 08-Jun-87 08:00:01 PDT +RequestArbiterFSM.bcd!5 08-Jun-87 08:00:22 PDT +WIGenerator.bcd!9 13-May-87 09:16:52 PDT +RAMControlFSM.bcd!12 08-Jun-87 08:00:04 PDT +ResponseChecker.bcd!5 13-May-87 09:20:36 PDT +ResponseCheckerImpl.bcd!10 08-Jun-87 08:00:39 PDT MC.dale!70 08-Jun-87 15:26:45 PDT MCDataPath.dale!7 08-Jun-87 12:53:25 PDT MCDataPath.cm!2 26-May-87 07:10:04 PDT +MCWireIcons.bcd!4 08-Jun-87 08:00:45 PDT +MCEccImpl.bcd!1 08-Jun-87 13:32:15 PDT Directory [Indigo]<Dragon>MemoryController> DRamImpl.mesa!13 13-May-87 09:14:07 PDT TestMC.mesa!46 08-Jun-87 17:36:10 PDT TestECC.mesa!6 24-Apr-87 08:07:57 PDT CommandDecodeFSM.mesa!15 15-Apr-87 09:56:31 PDT RequestQueueFSM.mesa!3 09-Sep-86 17:01:26 PDT ReplyControlFSM.mesa!14 13-Apr-87 17:40:07 PDT RequestArbiterFSM.mesa!2 10-Apr-87 14:37:20 PDT RAMControlFSM.mesa!3 11-May-87 11:47:54 PDT ResponseCheckerImpl.mesa!5 06-May-87 17:56:34 PDT ResponseChecker.mesa!3 05-May-87 17:50:17 PDT MCWireIcons.mesa!2 22-May-87 09:30:19 PDT MCEccImpl.mesa!1 08-Jun-87 13:32:05 PDT WIGenerator.mesa!4 07-May-87 16:34:57 PDT MC.cm!19 08-Jun-87 13:43:16 PDT SaveCoreMC.cm!1 12-Sep-86 15:46:01 PDT RestoreCoreMC.cm!1 12-Sep-86 17:35:32 PDT SimulateMC.cm!10 08-Jun-87 17:20:31 PDT StartTest.cm!1 12-May-87 10:06:40 PDT RollbackMC.cm!4 15-Oct-86 16:40:20 PDT DPRam.dale!3 09-Dec-86 12:28:49 PST MemoryControllerSpec.tioga!1 24-Sep-86 16:47:36 PDT MemoryControllerSpec.press!1 24-Sep-86 16:09:30 PDT MCBlockDiagram.dale!1 24-Sep-86 09:25:53 PDT MCBlockDiagram.interpress!1 24-Sep-86 16:51:10 PDT MCPinOut.dale!1 24-Sep-86 16:43:41 PDT MCPinOut.interpress!1 24-Sep-86 16:44:47 PDT Exports Imports [Indigo]<Dragon7.0>Top>Arbiter25.df Of ~= Using [ArbBasic25.dale, Arbiter.bcd, ArbiterImpl.bcd, ArbDBusImpl.bcd, ArbRandReq.bcd, ArbBasic25.install] Exports Imports [Cedar]<CedarChest7.0>Top>Graphs0.df Of ~= Using [FifoQueue.bcd, +FifoQueueImpl.bcd, FifoQueue.Install] Imports [Indigo]<Dragon>Top>DynaBus.df Of ~= Using [DynaBusInterface.bcd, +DynaBusInterfaceImpl.bcd] Imports [DATools]<DATools7.0>Top>Boole.df Of ~= Using [Boole.bcd, BooleCore.bcd, FiniteStateAutomata.bcd] Imports [DATools]<DATools7.0>Top>Core.df Of ~= Using [BitOps.bcd, Core.bcd, CoreClasses.bcd, CoreCreate.bcd, CoreFlat.bcd, CoreOps.bcd, CoreProperties.bcd] Imports [DATools]<DATools7.0>Top>CDCommon25.df Of ~= Using [CD.bcd, CDCells.bcd, CDCommandOps.bcd, CDIO.bcd, CDProperties.bcd, CDSequencer.bcd, CDViewer.bcd, D2Basic.bcd] Imports [DATools]<DATools7.0>Top>D2Basic3.df Of ~= Using [D2Orient.bcd] Imports [DATools]<DATools7.0>Top>Extract.df Of ~= Using [Sisyph.bcd, WireIcons.bcd] Imports [DATools]<DATools7.0>Top>Rosemary.df Of ~= Using [Rosemary.bcd, RosemaryUser.bcd, RosemaryVector.bcd, Ports.bcd] Imports [Cedar]<CedarChest7.0>Top>TerminalIO.df Of ~= Using [TerminalIO.bcd] Imports [Cedar]<Cedar7.0>Top>BootPackages.df Of ~= Using [CardTab.bcd, Random.bcd] Imports [Cedar]<Cedar7.0>Top>IO.df Of ~= Using [IO.bcd] Imports [Cedar]<Cedar7.0>Top>MesaRuntime.df Of ~= Using [Basics.bcd] Imports [Cedar]<Cedar7.0>Top>Rope.df Of ~= Using [Rope.bcd] --private copy until Louis fixes the real one Exports [Indigo]<Dragon>MemoryController> LogicMemImpl.mesa!1 13-Apr-87 14:42:56 PDT +LogicMemImpl.bcd!3 08-Jun-87 14:02:22 PDT Imports [DATools]<DATools7.0>Top>CellLibraries.df Of ~= Using [Logic.bcd, LogicUtils.bcd]