[Indigo]<Dragon>Top>IFUNotes.tioga!7

IFUNotes.tioga

Last Edited by Curry January 18, 1985 5:40:30 pm PST

Notes: January 25, 1985 10:09:23 am PST

noBypassing
passrt

Let dump dEXCH. It's odd, requires a unique output and doesn't help much.

instr ← And[current, BE[m:[op: InstrTopSig[8]], d:[op: dEXCH]]];

Set[s:instr, m:[state: ByteTopSig[8]], d:[state: 0], out:[

dontGetNextMacro: TRUE,

bReg: abStackTop,

cReg: [ s, minus1 ] ] ];

Set[s:instr, m:[state: ByteTopSig[8]], d:[state: 1], out:[

noBypassing: TRUE,

bReg: [ s, minus1 ],

cReg: cStackTop ]];

Notes: January 23, 1985 2:32:54 pm PST

DragOpsCross.Inst[dKFC]

DragOpsCross.Inst[dRETK] RETT

DragOpsCross.Inst[dLIP] LIFUR

DragOpsCross.Inst[dSIR] SIFUR

DragOpsCross.Inst[dSFP] FP

DragOpsCross.Inst[dFLOP] -- no FLIP change DragonFP and DragOps.tioga

FLOP

How about changing pushpending/poppending/empty to WillBeEmpty/ReturnReady

Status

trap/usermode changes at lev 0 (and need restart from lev 3)

reschedule changes at lev 3

fp changes at lev 3

Status must watch fp Shadow cAddrs

FPControl must use WtMode (cAddr match) to also or with CSWtAlt/Mult

Remember to include fpEnable pin

These two can be generated in the PLA or at end

out.kIsRtOp ← out.xaSource IN [alpha..bReg] AND (out.aluOp # FOPK);

out.DrKaLev2 ← out.xaSource IN [alpha..bReg] or fp..... See notes;

Notes: January 21, 1985 1:50:59 pm PST

Remove PCNext from InstrDecodeOut

pcNext-Is-pcBus ← macroJump OR dontGetNextMacro;

Mode change could be simply SPR to ifuFPModeAlu or ifuFPModeMult if there were not the requirement to catch fp ops in the case where the fpEnable pin is not true.

Notes: January 18, 1985 4:23:02 pm PST

Reorder traps - IFUPLA.ExceptionCode

trap expansions for cTrap fpFault epFault

4 bit Dragon.PBusFaults

Redefinition of Dragon.PBusFaults

PBusFaults: TYPE = MACHINE DEPENDENT {

FPeqZeroE, FPlsInfE, FPgrNEZeroE, FPneZeroI,

FPres4, FPoFlowI, FPuFlow, FPuFlowI,

FPaDeNorm, FPbDeNorm, FPabDeNorm, FPdivByZero,

FPaNaN, FPbNaN, FPabNaN, FPinvalid};

None: PBusFaults = FPeqZeroE;

Page: PBusFaults = FPlsInfE;

Write: PBusFaults = FPgrNEZeroE;

Redefinition of Dragon.PBusCommands

PBusCommands: TYPE = MACHINE DEPENDENT {NoOp(0), Reserve1(1), FPLdAlu(2), FPLdMult(3), FPUnAlu(4), FPUnMult(5), FPXfrMult(6), FPXfrMult(7), Store(8), Fetch(9), StoreHold(10), FetchHold(11), IOStore(12), IOFetch(13), IOStoreHold(14), IOFetchHold(15)};

0000 NoOp

0001

0010 FPLdAlu CSLd 3 XaDr 3 euWt

0011 FPLdMult CSLd 3 XaDr 3 euWt

0100 FPUnAlu CSUn 2 XaDr 2 NoCheckParity

0101 FPUnMult CSUn 2 XaDr 2 NoCheckParity

0110 FPXfrAlu CSUn 2 XaDr 2 3 NoCheckParity

0111 FPXfrMult CSUn 2 XaDr 2 3 NoCheckParity

1000 Store

1001 Fetch

1010 StoreHold

1011 FetchHold

1100 IOStore

1101 IOFetch

1110 IOStoreHold

1111 IOFetchHold

CSUnAlu ← FPUnAlu OR FPXfrAlu

CSUnMult ← FPUnMult OR FPXfrMult

CSLdAlu ← FPLdAlu OR FPXfrAlu OR Caddr fpModeAlu

CSLdMult ← FPUnMult OR FPXfrMult OR Caddr fpModeMult

XaDr2 ← FPUnAlu .. FPXfrMult OR XaSource abgd..alpha

XaDr3 ← FPLdAlu .. FPLdMult, OR FPXfrAlu .. FPXfrMult

euDrPBus ← FPLdAlu .. FPLdMult OR *Store*

CheckParity ← *Fetch*

IFUPLA.XaSource

This is essentially the Load-Unload code for the Weitek chips with alpha-beta-gamma-delta selection stuck into gaps in the encoding. See DragonIFU33.sil

Note: alpha-beta-gamma-delta selection must => DrXa2

XaSource: TYPE = MACHINE DEPENDENT {

none(00B),

fpLdSglBSt(06B), fpLdLswBSt(12B), fpLdMswBSt(16B),

delGamBetAlp(20B), betaAlpha(21B), beta(22B), alpha(23B),

fpLdSglAUnMsw(25B), fpLdLswAUnLsw(30B), fpLdMswAUnMsw(35B), res31(37B)};

ProcessorRegister: TYPE = MACHINE DEPENDENT {

euJunk (128), -- the non-matching EU register

(129)

euMAR (130), -- MemoryAddressRegister

euField (131), -- Field register

fpAluClear (132), -- Base of FP Alu shadow Regs can alias 134 in EU

fpAluSgl (133), -- Single precision shadow can alias 135 in EU

fpAluLsw (134), -- Double precision Lsw shadow can alias 132 in EU

fpAluMsw (135), -- Double precision Msw shadow can alias 133 in EU

(136)

(137)

(138)

(139)

fpMultClear (140), -- Base of FP Mult shadow Regs can alias 142 in EU

fpMultSgl (141), -- Single precision shadow can alias 143 in EU

fpMultLsw (142), -- Double precision Lsw shadow can alias 140 in EU

fpMultMsw (143), -- Double precision Msw shadow can alias 141 in EU

euConstant (144), -- Base of EU constant registers (12 regs)

(156)

(157)

(158)

(159)

euAux (160), -- Base of EU aux registers (16 regs)

euBogus (176), -- [euBogus..euLast] not legal (NA) (63 regs)

euLast (239), -- last possible EU reg (NA)

ifuXBus (240), -- Base for IFU regs

ifuStatus (241), -- IFU status

ifuFPModeAlu (242), -- floating point mode register

ifuFPModeMult (243), -- floating point mode register

ifuFPMaskFlags (244), -- floating point mask and flags

ifuSLimit (245), -- stack limit register

ifuYoungestL (246), -- youngest L in IFU stack

ifuYoungestPC (247), -- youngest PC in IFU stack

ifuEldestL (248), -- eldest L in IFU stack

ifuEldestPC (249), -- eldest PC in IFU stack (rd removes, wt adds)

(250)

ifuBogus (251), -- [ifuBogus..ifuLast] are not legal (NA)

ifuL (252), -- current L register (NA)

ifuS (253), -- current S register (NA)

ifuPC (254), -- current program counter (NA)

ifuLast (255)};-- last possible IFU reg (NA)

IFUPLA

32 KBus = INT[32], -- PhA bidirectional, PhB A,B,C to EU

02 EUAluLeftSrcBA > EnumType["Dragon.ALULeftSources"],

02 EUAluRightSrcBA > EnumType["Dragon.ALURightSources"],

02 EUStore2ASrcBA > EnumType["Dragon.Store2ASources"],

05 EUAluOpAB > EnumType["Dragon.ALUOps"],

04 EUCondSelAB > EnumType["Dragon.CondSelects"],

01 EUHoldCarryBA > BOOL,

01 EUSt3AisCBusBA > BOOL,

01 EURes3AisCBusBA > BOOL,

01 EUConditionBA < BOOL,

01 EURes3BisPBusAB > BOOL,

01 EUWriteToPBusAB > BOOL,

01 EUCheckPParityAB > BOOL,

---

22

04 FPStatusB <EnumType["DragonFP.Status"],

01 FPCSLoadBA >EnumType["DragonFP.CSLoad"],

01 FPCSUAluBA >EnumType["DragonFP.CSUnload"],

01 FPCSUMultBA >EnumType["DragonFP.CSUnload"],

---

07

04 EPCmdA >EnumType["Dragon.PBusCommands"],

01 EPRejectB =BOOL, -- driven by IFP

03 EPFaultB =EnumType["Dragon.PBusFaults"], -- driven by IFP

32 IPData =INT[32], -- address PhA, data PhB

04 IPCmdA >EnumType["Dragon.PBusCommands"],

01 IPRejectB <BOOL,

03 IPFaultB <EnumType["Dragon.PBusFaults"],

01 IPParityB <BOOL,

01 IPNPErrorB =BOOL,

01 ResetAB <BOOL,

01 DHoldAB <BOOL,

01 DShiftAB <BOOL,

01 DExecuteAB <BOOL,

01 DNSelectAB <BOOL,

01 DDataInAB <BOOL,

01 DDataOutAB =BOOL,

01 RescheduleAB <BOOL,

01 PhA <BOOL,

01 PhB <BOOL,

---

121

MDF becomes just Field - eu bypassing used as temp register for Mul and Div

MQ no longer addressable:

MQ is not considered part of processor state

It is not addressed with LEUR/SEUR or LIFUR/SIFUR instructions

It is only used as a temp register for mult and div which are autonomous instructions

It is loaded by the microcode using the alu op PassLtWtMQ (bypassing not affected)

It is read by the microcode using the alu op RdMQ

Multiply

Step 0 - Load 0 into R1, Multiplier into MQ, initialize MultiplicandSign flag and branch out if zero

Unsigned

Lt ← S=Multiplicand

Rt ← S-1=Multiplier

aluop ← MulLdU

MicroBranch if aluout=0 (the product sign logic won't work if the M'cand=0)

R1 ← 0

MQ ← Multiplier

MCandS ← FALSE

ProdS ← FALSE

lastWasSub ← FALSE

S-1 = Product.msw ← R1

Signed

Lt ← S=Multiplicand

Rt ← S-1=Multiplier

aluop ← MulLdS

aluout ← Lt

MicroBranch if aluout=0 (the product sign logic won't work if the M'cand=0)

R1 ← 0

MQ ← Multiplier

MCandS ← LtSign

ProdS ← FALSE

lastWasSub ← FALSE

S-1 = Product.msw ← R1

Step 1..16

zero ← 000 or 111

two ← 100 or 011

sub ← 1xx

Lt ← S-1=Product.msw (right shift if two) (use old ProdS to do sign extend)

Rt ← S=Multiplicand or 0 (0 if zero)

aluop ← MulStep

aluout ← Lt (+/-) Rt - if sub

ProdS ← zero AND ProdS OR ~zero AND (sub xor MCandS)

R1|MQ ← aluout|Rt rt shift 1 if two and 2 if not (use new ProdS to do sign extend)

S-1=Product.msw ← R1

Step 17

Unsigned

zero ← xx0

Lt ← S-1=Product.msw

Rt ← S=Multiplicand or 0 (0 if zero)

aluop ← MulAdj

aluout ← Lt + Rt

MQ ← MQ

R1 ← aluout

S-1=Product.msw ← R1

Signed

instruction done

aluop ← RdMQ

S=Product.lsw ← MQ

Step 18 Unsigned

instruction done

aluop ← RdMQ

S=Product.lsw ← MQ

MicroBranch 1

instruction done

Lt ← S=Multiplicand = 0

Rt ← 0

aluop ← OR

aluout ← Lt

S-1 = Product.msw ← R1

Divide

Step 0

Lt ← S-2=Dividend MSW

Rt ← S-1=Dividend LSW

aluop ← DivLdDbl

aluout ← Lt

R1 ← aluout

MQ ← Rt

Zero ← FALSE

S+1=temporary Remainder location ← R1

Step 1

Unsigned

Lt ← S+1 = temporary Remainder location

Rt ← S = Divisor

aluop ← DivLdU

Cry aluout ← Lt-Rt (result must be negative)

TRAP if Cry

DivisorSign ← FALSE

DividendSign ← FALSE

Zero ← (aluout=0 OR Zero) AND MQSign

R1 | MQ ← LShift[ aluout | MQ | DivisorSign#Cry] (next op quaranteed to be add)

S+1=temporary Remainder location ← R1

Signed

Lt ← S+1 = temporary Remainder location

Rt ← S = Divisor

aluop ← DivLdS

aluout ← Lt

Cry ← ~ LtSign

DivisorSign ← RtSign

DividendSign ← LtSign

Zero ← (aluout=0 OR Zero) AND MQSign

R1 | MQ ← LShift[ aluout | MQ | DivisorSign#Cry]

S+1=temporary Remainder location ← R1

Step 2

Unsigned

Lt ← S+1 = temporary Remainder location

Rt ← S = Divisor

aluop ← DivStep

Cry aluout ← Lt (+/- - if MQSign) Rt

Zero ← (aluout=0 OR Zero) AND MQSign

R1 | MQ ← LShift[ aluout | MQ | DivisorSign#Cry]

S-1=Remainder ← R1

Signed

Lt ← S+1 = temporary Remainder location

Rt ← S = Divisor

aluop ← DivStep

Cry aluout ← Lt (+/- - if MQSign) Rt

TRAP IF

aluout=0 AND (DividendSign = DivisorSign)

aluout#0 AND (DividendSign # Cry)

Zero ← (aluout=0 OR Zero) AND MQSign

R1 | MQ ← LShift[ aluout | MQ | DivisorSign#Cry]

S-1=Remainder ← R1

Step 3..n

Lt ← S-1=Remainder

Rt ← S = Divisor

aluop ← DivStep

Cry aluout ← Lt (+/- - if MQSign) Rt

Zero ← (aluout=0 OR Zero) AND MQSign

R1 | MQ ← LShift[ aluout | MQ | DivisorSign#Cry]

S-1=Remainder ← R1

Step n+1

MDiv

Lt ← S-1=Remainder

Rt ← S = Divisor

aluop ← DivAdjM

Cry aluout ← Lt (+/- - if MQSign) Rt

Zero ← (aluout=0 OR Zero) (Update Zero before use below)

RemCorFF ←

~DivisorSign ~Cry OR

DivisorSign Cry ~Zero OR

~Cry Zero OR

QCorFF ←

DivisorSign Zero

R1 ← aluout

MQ ← LShift[ MQ | DivisorSign#Cry]

S-1=Remainder ← R1

RDiv

Lt ← S-1=Remainder

Rt ← S = Divisor

aluop ← DivAdjR

Cry aluout ← Lt (+/- - if MQSign) Rt

Zero ← (aluout=0 OR Zero) (Update Zero before use below)

RemCorFF ←

~DividendSign ~Cry OR

DividendSign Cry ~Zero OR

~Cry Zero OR

QCorFF ←

DivisorSign Zero OR

~DividendSign DivisorSign OR

DividendSign ~DivisorSign ~Zero

R1 ← aluout

MQ ← LShift[ MQ | DivisorSign#Cry]

S-1=Remainder ← R1

Step n+2

Lt ← S-1=Remainder

Rt ← 0 OR S=Divisor (IF RemCorFF)

aluop ← DivAdj

*** aluout ← Lt (+/- - if MQSign) Rt

Cry ← QCorFF

R1 ← aluout

MQ ← MQ

S-1=Remainder ← R1

Step n+3

R1 ← MQ

S-2=Quotient ← R1

Step n+4

Lt ← S-2=Quotient

Rt ← 0

Cry aluout ← Lt + Rt + Cry

R1 ← aluout

S-2=Quotient ← R1

FP and Fixed Mult/DivChanges

Notes to Russ

New DragOpsCross.ProcessorRegister

euStack (000), -- base of EU stack (128 regs)

euJunk (128), -- the non-matching EU register

eu129 (129), -- easily addressable spare (NA)

euMAR (130), -- MemoryAddressRegister

euField (131), -- Field register

euAux (132), -- base of EU auxilliary registers (16 regs)

eu148 (148), -- easily addressable spare (NA)

eu149 (149), -- easily addressable spare (NA)

eu150 (150), -- easily addressable spare (NA)

eu151 (151), -- easily addressable spare (NA)

euConstant (152), -- base of EU constant registers (12 regs)

euBogus (169), -- [euBogus..euLast] are not legal (NA)

euLast (239), -- last possible EU reg (NA)

ifuXBus (240), -- internal IFU register (X bus)

ifuLevel3LS (241), -- internal IFU register (level 3 L & S)

ifuYoungestL (242), -- youngest L in IFU stack

ifuYoungestPC (243), -- youngest PC in IFU stack

ifuEldestL (244), -- eldest L in IFU stack

ifuEldestPC (245), -- eldest PC in IFU stack (read removes, write adds)

ifuStatus (246), -- IFU status

ifuSLimit (247), -- stack limit register

ifuFPMaskFlags (248), -- floating point mask and flags

ifuFPMode (249), -- floating point mode register

ifuBogus (250), -- [ifuBogus..ifuLast] are not legal (NA)

ifu251 (251), -- easily addressable spare (NA)

ifuL (252), -- current L register (NA)

ifuS (253), -- current S register (NA)

ifuPC (254), -- current program counter (NA)

ifuLast (255) -- last possible IFU reg (NA)

New OB OpCode: FP

Redefined OpCode: DIV Quotient|Remainder = [S-2]|[S-1] ← [S-2][S-1]/[S-0] S←S-1

Change stack limit from 17 to 16

FP and Fixed Mult/DivChanges

Lizard

Mult, Div and FPOp's

Change stack limit from 17 to 16 when Russ does

DragOpsCross

DragOpsCross.ProcessorRegister {fpMaskFlags fpMode}

Dragon

add FPFault to Dragon.PBusFaults

add StoreFP, FetchFPAlu and FetchFPMult to PBusCommands

New EU ops: PassRt, PassLt, PassLtWtMQ, RdMQ, DivLast (MulStep and DivStep already there)

DragonImpl

DragonIFU

add spaces after :'s in DragonIFU

change euCacheCmd to euPBusCmd

DragonIFUImpl

add StoreFP, FetchFP* PBusCommands to IsRdCmd and IsWtCmd

DragonFP.mesa

DragonFPImpl.mesa

DragonMicrocode

change euCacheCmd to euPBusCmd

add XASources (7+9=16 => add one bit):

fpLdMode,

fpLdAMsw, fpLdALsw,

fpLdBMsw, fpLdBLsw,

fpUlMsw, fpUlLsw

DragonMicrocodeImpl

add FPOP

add MULT

add DIV

DragOpsCross.JBBformatRange => {

rj: DragOpsCross.RJBformat these can be removed

TRUSTED {rj ← LOOPHOLE[instruction]}; these can be removed

IFU Page Fault Must wait for possible CJump or MemRefFault to execute

Can XOP be one cycle

IFU

change EUWriteToCacheAB to EUWriteToPBusAB

add

FPStatusB >EnumType["DragonFP.Status"],

FPCSLoadAB <EnumType["DragonFP.CSLoad"],

FPCSUAluAB <EnumType["DragonFP.CSUnload"],

FPCSUMultAB <EnumType["DragonFP.CSUnload"]

IFetcher

IDecoder

Change stack limit from 17 to 16 when Russ does

IRegAddr

IPipe

Use PassRt EU Op

add

FPStatusB >EnumType["DragonFP.Status"],

FPCSLoadAB <EnumType["DragonFP.CSLoad"], function of PBusCmnds

FPCSUAluAB <EnumType["DragonFP.CSUnload"], function of PBusCmnds

FPCSUMultAB <EnumType["DragonFP.CSUnload"] function of PBusCmnds

add KBus drivers for fpControl

New EU ops: PassRt, PassLtWtMQ, RdMQ, DivLast

IStack

IFP

FP

add logging stuff

EU

EUWriteToPBusAB

New EU ops: PassRt, PassLtWtMQ, RdMQ, Mult, Div DivLast

KBus during Phase A

It is the responisbility of the Microcode (using multicycles) to insure that there is no conflict for the KBus when it is used at level 4 to move data from the EU to the IFU. SIFUR instructions are assessed a 3 cycle penalty by this requirement. Since the other instructions using the KBus at level4 (SJ, SFC and SFCI) are branching instructions, there is no penalty. When the KBus is used in this way, the CAddr passed to the EU in the previous phase B is in the range of IFU Registers.

KBus conflicts caused by FP ops should never happen since the load signals are driven from level3 and the unload signals from level 2 (just like EUAluRtIsK).

Floating Point operation

The two floating point chips operate using a single phase clock which makes it's active transition between PhA and PhB. In order to save about 12 to 15 pins (3 pins redundant), the KBus is used during PhA to move the load[0..5], unload[0..2] and function[0..5] signals from the IFU to the FP chips. The 3 ChipSelect signals are driven over separate pins.

Reject and Fault occuring in the instruction preceding a FP op are handled correctly (it says here). That is, the Load Chip Select signal is disabled during the next A,B cycle and the IFP section of the IFU knows to ignore a set mode function.

The only guaranteed state associated with FP operations is the Mode, Mask and Flag registers. There are no FP ops which allow 'partial' operations which assume the previous state of internal FP chip registers (ie AM, AL, BM, BL etc). Each FP op loads all its operands from the stack, waits a function specific numer of cycles then moves any results back to the stack.

IFP

The IFP is a section of the IFU which deals with two sets of data:

It maintains a copy of the mode register.

Write: The mode register is written as a side affect of setting the mode registers in the two FP chips. When both the high order Function bits (FPAlu, FPMult) are set and FPCSLoad is enabled then Function is interpreted as a new nibble in the Mode register as described in the Weitek documentation.

Read: The mode register may be read using a LIFUR instruction (Lev0BAddr matches FPMode).

It maintains copies of the 16 bit Mask and Flag registers and issues Reject and FPFfault.

Write: CSUnLoad during PhA causes the floating point Status signals during PhB (1.5 cycles later) to be decoded. The three unsticky flags (used for legal floating point comparisons) are cleared and the flag corresponding to the decoded status signal is set. If any of the curent flags are not masked then Reject and FPFault are asserted. The reject causes the EU to freeze and not store the FP data currently on the PBus, and the fault causes the IDecoder logic during the next phase A to generate a FP trap exception.

Write: The Mask and Flag registers may also be written using a SIFUR instruction (Lev3Caddr matches FPMaskFlag).

Read: The Mask and Flag registers may be read using a LIFUR instruction (Lev0BAddr matches FPMaskFlag).

FP format: FP alpha

alpha: BYTE = FPMult: BOOL, FPAlu: BOOL, FPFunction: CARDINAL[0..64)

IF FPMult AND FPAlu

THEN Set Mode

ELSE Execute FPFunction for specified device. (one BOOL must be TRUE)

Binary op operands (A op B) are stacked in the EU with A pushed first.

Double precision operands are stacked in the EU with the most significant word pushed first.

alpha for ALU OPs

Subtract Compare (returns only status)

01 00 000 0 F32 - F32 01 10 000 0 F32 - F32

01 00 000 1 F64 - F64 01 10 000 1 F64 - F64

01 00 001 0 |F32 - F32| 01 10 001 0 -F32 + F32

01 00 001 1 |F64 - F64| 01 10 001 1 -F64 + F64

01 00 010 0 01 10 010 0 |F32| - |F32|

01 00 010 1 01 10 010 1 |F64| - |F64|

01 00 011 0 01 10 011 0

01 00 011 1 01 10 011 1

01 00 100 0 -F32 + 0 01 10 100 0 F32 - 0

01 00 100 1 -F64 + 0 01 10 100 1 F64 - 0

01 00 101 0 01 10 101 0

01 00 101 1 01 10 101 1

01 00 110 0 -F32 + 0 01 10 110 0

01 00 110 1 -F64 + 0 01 10 110 1

01 00 111 0 01 10 111 0

01 00 111 1 01 10 111 1

Add Convert

01 01 000 0 F32 + F32 01 11 000 0 U32 to D32 (exact)

01 01 000 1 F64 + F64 01 11 000 1 U64 to D64 (exact)

01 01 001 0 |F32 + F32| 01 11 001 0 D32 to W32

01 01 001 1 |F64 + F64| 01 11 001 1 D64 to W64

01 01 010 0 |F32| + |F32| 01 11 010 0 U32 to D32 (inexact)

01 01 010 1 |F64| + |F64| 01 11 010 1 U64 to D64 (inexact)

01 01 011 0 01 11 011 0

01 01 011 1 01 11 011 1

01 01 100 0 F32 + 0 01 11 100 0 F32 - I32

01 01 100 1 F64 + 0 01 11 100 1 F64 - I32

01 01 101 0 01 11 101 0 I32 - F32

01 01 101 1 01 11 101 1 I32 - F64

01 01 110 0 |F32| + 0 01 11 110 0 F32 - F64

01 01 110 1 |F64| + 0 01 11 110 1 F64 - F32

01 01 111 0 01 11 111 0

01 01 111 1 01 11 111 1

alpha for Mult OPs

10 xxx 000 F32 * F32

10 xxx 001 F64 * F64

10 xxx 010 W32 * F32

10 xxx 011 W64 * F64

01 xxx 100 F32 * W32

01 xxx 101 F64 * W64

01 xxx 110 W32 * W32

01 xxx 111 W64 * W64

10 000 xxx A * B

10 001 xxx |A| * B

10 010 xxx A * |B|

10 011 xxx |A| * |B|

01 100 xxx - A * B

01 101 xxx -|A| * B

01 110 xxx - A * |B|

01 111 xxx -|A| * |B|

alpha for Set Mode

1100RRIF = mode0

RR Floating point rounding mode

00 Round toward nearest

01 Round toward zero

10 Round toward Positive infinity

11 Round toward negative infinity

I Fixed point rounding mode

0 Round according to Floating point rounding mode

1 Round toward zero

F Fast mode (this is not in the doc but is supposed to exist)

0 IEEE mode

1 Flush denormalized operands and results to zero

1101AAxx = mode1

AA Multiplier Accumulation rate (does this really exist?)

00 Clock/1

01 Clock/2

10 Clock/3

11 Clock/4

Types of FPFunctions => separate decoding in the Decoder PLA

Operands Result Time Cycles

Set Mode - - 120ns 2

Convert Unary Single one Single Double 240ns 3

Convert Unary Double one Double Single 240ns 3

Compare Unary Single one Single - 240ns 3

Compare Unary Double one Double - 240ns 3

Compare Binary Single two Single - 240ns 3

Compare Binary Double two Double - 240ns 3

Alu Unary Single one Single Single 240ns 3

Alu Unary Double one Double Double 240ns 3

Alu Binary Single two Single Single 240ns 3

Alu Binary Double two Double Double 240ns 3

Mult Binary Single two Single Single 240ns 3

Mult Binary Double two Double Double 360 ns 4

Cycle 0 1 2 3 4 5 6 7 8 9

sglUnCom AM<S0 Stat S←S-1

sglUnAlu AM<S0 S0<AM S←S-0

sglUnCvt AM<S0 S0<AM S+<AL S←S+1

dblUnCom AL<S0 AM<S1 Stat S←S-2

dblUnAlu AL<S0 AM<S1 S1<AM S0<AL S←S-0

dblUnCvt AL<S0 AM<S1 S1<AM S←S-1

sglBiCom BM<S0 AM<S1 Stat S←S-2

sglBiAlu BM<S0 AM<S1 S1<AM S←S-1

sglBiMul BM<S0 AM<S1 S1<MM S←S-1

dblBiCom BL<S0 BM<S1 AL<S2 AM<S3 Stat S←S-4

dblBiAlu BL<S0 BM<S1 AL<S2 AM<S3 S3<AM S2<AL S←S-2

dblBiMul BL<S0 BM<S1 AL<S2 AM<S3 S3<MM S2<ML S←S-2

01 00 0. .0 sglBiAlu

01 00 0. .1 dblBiAlu

01 00 1. .0 sglUnAlu

01 00 1. .1 dblUnAlu

01 01 0. .0 sglBiAlu

01 01 0. .1 dblBiAlu

01 01 1. .0 sglUnAlu

01 01 1. .1 dblUnAlu

01 10 0. .0 sglBiCom

01 10 0. .1 dblBiCom

01 10 1. .0 sglUnCom

01 10 1. .1 dblUnCom

01 11 0. .0 sglUnAlu

01 11 0. .1 dblUnAlu

01 11 10 00 sglUnAlu

01 11 10 01 dblUnCvt

01 11 10 10 sglUnAlu

01 11 10 11 sglUnCvt

01 11 11 00 sglUnCvt

01 11 11 01 dblUnCvt

01 11 11 10 *

01 11 11 11 *

10 .. .. .0 sglBiMult

10 .. .. .1 dblBiMult

11 .. .. .. dblBiMult

**************

01 00 0. .0 sglBiAlu

01 01 0. .0 sglBiAlu

01 00 1. .0 sglUnAlu

01 01 1. .0 sglUnAlu

01 11 0. .0 sglUnAlu

01 11 10 00 sglUnAlu

01 11 10 10 sglUnAlu

01 00 1. .1 dblUnAlu

01 01 1. .1 dblUnAlu

01 11 0. .1 dblUnAlu

01 00 0. .1 dblBiAlu

01 01 0. .1 dblBiAlu

01 10 0. .0 sglBiCom

01 10 0. .1 dblBiCom

01 10 1. .0 sglUnCom

01 10 1. .1 dblUnCom

01 11 10 11 sglUnCvt

01 11 11 00 sglUnCvt

01 11 10 01 dblUnCvt

01 11 11 01 dblUnCvt

01 11 11 10 *

01 11 11 11 *

10 .. .. .0 sglBiMult

10 .. .. .1 dblBiMult

11 .. .. .. dblBiMult

**************

01 0. 0. .0 sglBiAlu

01 0. 1. .0 sglUnAlu

01 11 0. .0 sglUnAlu

01 11 10 .0 sglUnAlu

01 0. 1. .1 dblUnAlu

01 11 0. .1 dblUnAlu

01 0. 0. .1 dblBiAlu

01 10 0. .0 sglBiCom

01 10 0. .1 dblBiCom

01 10 1. .0 sglUnCom

01 10 1. .1 dblUnCom

01 11 1. 11 sglUnCvt

01 11 11 .0 sglUnCvt

01 11 1. 01 dblUnCvt

10 .. .. .0 sglBiMult

10 .. .. .1 dblBiMult

11 .. .. .. dblBiMult

First 16 ALUOps 16 RR instructions 300B - 317B
Or (0) op47 dROR dRRX (gets mapped to VAdd)
And (1) BndChk dRAND dRBC
Xor (2) UAdd dRXOR dRUADD
(3) USub dRUSUB
FOP (4) VAdd dRFU dRVADD
FOPK (5) VSub dRVSUB
SAdd (6) LAdd dRADD dRLADD
SSub (7) LSub dRSUB dRLSUB

dRBC also get BC condition select

False (0) x
EZ (1) dRJEB
LZ (2) dRJLB
LE (3) dRJEB

True (4) dRJEB
NE (5) dRJEB
GE (6) dRJEB
GZ (7) dRJEB

OvFl (8)
BC (9)
IL (10)
DivOvFl (11)

NotOvFl (12)
NotBC (13)
NotIL (14)
op57 (15)