PORTS [
Timing and housekeeping interface
PhA, nPhA, PhB, nPhB<BOOL,
Vdd, Gnd<BOOL,
nBoardError=BOOL, -- Tristate
Main memory interface
MHold, MnReset<BOOL,
MnRq>BOOL,
MnGnt<BOOL,
MnNewRq>BOOL, -- Tristate
MnAdCycle=BOOL,
MTransport=INT[36],
MParity=BOOL,
MnShared=BOOL,
MnAbort>BOOL, -- Tristate
MnHousekeepingInProgress=BOOL,
MnDV=BOOL,
Serial debugging interface
DShift<BOOL,
DExecute<BOOL,
DnSelect0, DnSelect1, DnSelect2, DnSelect3, DnSelect4<BOOL,
DDataIn<BOOL,
DDataOut>BOOL, -- Tristate
IFU interface
IPData=INT[32],
IPParityB=BOOL,
IPCmdA<EnumType["Dragon.PBusCommands"],
IPRejectB>BOOL, -- Tristate
IPFaultB>EnumType["Dragon.PBusFaults"], -- Tristate
EU interface
EPData=INT[32],
EPParityB=BOOL,
EPCmdA<EnumType["Dragon.PBusCommands"],
EPRejectB>BOOL, -- Tristate
EPFaultB>EnumType["Dragon.PBusFaults"] -- Tristate
]
Expand
Internal M bus
IMnMRq0, IMnMRq1, IMnMRq2, IMnMRq3: BOOL;
IMnRq0, IMnRq1, IMnRq2, IMnRq3: BOOL;
IMnGnt0, IMnGnt1, IMnGnt2, IMnGnt3: BOOL;
IMnNewRq: BOOL; -- Tristate
IMnAdCycle: BOOL;
IMTransport: INT[36];
IMParity: BOOL;
IMnShared: BOOL;
IMnAbort: BOOL; -- Tristate
IMnHousekeepingInProgress: BOOL;
IMnDV: BOOL;
RAM control
RAddress: INT[14];
RnCS: BOOL;
RnWE: BOOL;
Hack
Vdd4: INT[4]; -- dump this when Rosemary 3.0 surfaces
euc0: DataCache[PadVdd: Vdd, PadGnd: Gnd, PData: EPData, PParityB: EPParityB, PCmdA: EPCmdA, PRejectB: EPRejectB, PFaultB: EPFaultB, PnPError: nBoardError, MnRq: IMnRq0, IMnMRq: IMnMRq0, MnGnt: IMnGnt0, MnNewRq: IMnNewRq, MnAdCycle: IMnAdCycle, MTransport: IMTransport, MParity: IMParity, MnShared: IMnShared, MnAbort: IMnAbort, MnHousekeepingInProgress: IMnHousekeepingInProgress, MnError: nBoardError, MnDV: IMnDV, DnSelect: DnSelect0, PWriteEnable: Vdd4, PInternalParity: Gnd];
euc1: DataCache[PadVdd: Vdd, PadGnd: Gnd, PData: EPData, PParityB: EPParityB, PCmdA: EPCmdA, PRejectB: EPRejectB, PFaultB: EPFaultB, PnPError: nBoardError, MnRq: IMnRq1, IMnMRq: IMnMRq1, MnGnt: IMnGnt1, MnNewRq: IMnNewRq, MnAdCycle: IMnAdCycle, MTransport: IMTransport, MParity: IMParity, MnShared: IMnShared, MnAbort: IMnAbort, MnHousekeepingInProgress: IMnHousekeepingInProgress, MnError: nBoardError, MnDV: IMnDV, DnSelect: DnSelect1, PWriteEnable: Vdd4, PInternalParity: Gnd];
ifuc0: DataCache[PadVdd: Vdd, PadGnd: Gnd, PData: IPData, PParityB: IPParityB, PCmdA: IPCmdA, PRejectB: IPRejectB, PFaultB: IPFaultB, PnPError: nBoardError, MnRq: IMnRq2, IMnMRq: IMnMRq2, MnGnt: IMnGnt2, MnNewRq: IMnNewRq, MnAdCycle: IMnAdCycle, MTransport: IMTransport, MParity: IMParity, MnShared: IMnShared, MnAbort: IMnAbort, MnHousekeepingInProgress: IMnHousekeepingInProgress, MnError: nBoardError, MnDV: IMnDV, DnSelect: DnSelect2, PWriteEnable: Vdd4, PInternalParity: Gnd];
ifuc1: DataCache[PadVdd: Vdd, PadGnd: Gnd, PData: IPData, PParityB: IPParityB, PCmdA: IPCmdA, PRejectB: IPRejectB, PFaultB: IPFaultB, PnPError: nBoardError, MnRq: IMnRq3, IMnMRq: IMnMRq3, MnGnt: IMnGnt3, MnNewRq: IMnNewRq, MnAdCycle: IMnAdCycle, MTransport: IMTransport, MParity: IMParity, MnShared: IMnShared, MnAbort: IMnAbort, MnHousekeepingInProgress: IMnHousekeepingInProgress, MnError: nBoardError, MnDV: IMnDV, DnSelect: DnSelect3, PWriteEnable: Vdd4, PInternalParity: Gnd];
a0: AddressCache[PadVdd: Vdd, PadGnd: Gnd, MnError: nBoardError, DnSelect: DnSelect4, IMnError: nBoardError];
drop down 32 RAM chips
Cedar
This must be changed when Rosemary 3.0 is available to rip apart IMTransport for each of the RAM chips.
FOR i:
CARDINAL
IN [0..32)
DO
[] ← to.class.CellInstance[erInstance: to.instance, instanceName: IO.PutFR["cacheRAM%g", IO.int[i]], typeName: "HM6167", interfaceNodes: IO.PutFR["Din: IMTransport[%g], Dout: IMTransport[%g]", IO.int[i+4], IO.int[i+4]]];
ENDLOOP;
;
parityRAM: HM6167[Din: IMParity, Dout: IMParity]