MiscBoard.rose
Last Edited by: Barth, April 25, 1985 9:45:20 pm PST
CELLTYPE "MiscBoard"
PORTS [
Timing and housekeeping interface
PhA, nPhA, PhB, nPhB<BOOL,
Vdd, Gnd<BOOL,
Main memory interface
MHold, MnReset<BOOL,
MnRq0, MnRq1, MnRq2, MnRq3>BOOL,
MnGnt0, MnGnt1, MnGnt2, MnGnt3<BOOL,
MnNewRq>BOOL, -- Tristate
MnAdCycle=BOOL,
MTransport=INT[36],
MParity=BOOL,
MnShared=BOOL,
MnAbort>BOOL, -- Tristate
MnHousekeepingInProgress=BOOL,
MnError>BOOL, -- Tristate
MnDV=BOOL,
Serial debugging interface
DShift<BOOL,
DExecute<BOOL,
DSelectAdr<INT[12],
DDataIn<BOOL,
DDataOut>BOOL -- Tristate
]
Expand
This has VME to M bus, M bus to VME, clock generator, map cache, arbiter, and baseboard computer. Baseboard computer includes CPU, 1/2 MB RAM, boot ROM, disk, ethernet, keyboard, mouse and dumb B&W display controller.
ENDCELLTYPE