MemoryBoard.rose
Last Edited by: Barth, April 25, 1985 9:44:40 pm PST
CELLTYPE "MemoryBoard"
PORTS [
Timing and housekeeping interface
PhA, nPhA, PhB, nPhB<BOOL,
Vdd, Gnd<BOOL,
Main memory interface
MHold, MnReset<BOOL,
MnAdCycle=BOOL,
MTransport=INT[36],
MParity=BOOL,
MnAbort>BOOL, -- Tristate
MnError>BOOL, -- Tristate
MnDV=BOOL,
Serial debugging interface
DShift<BOOL,
DExecute<BOOL,
DSelectAdr<INT[12],
DDataIn<BOOL,
DDataOut>BOOL -- Tristate
]
Expand
memory chips, memory controller, dbus logic? perhaps inside chip
ENDCELLTYPE