> MHold, MnReset: BOOL; MnRq0, MnRq1, MnRq2, MnRq3, MnRq4, MnRq5, MnRq6, MnRq7, MnRq8, MnRq9, MnRq10, MnRq11, MnRq12, MnRq13, MnRq14, MnRq15: BOOL; MnGnt0, MnGnt1, MnGnt2, MnGnt3, MnGnt4, MnGnt5, MnGnt6, MnGnt7, MnGnt8, MnGnt9, MnGnt10, MnGnt11, MnGnt12, MnGnt13, MnGnt14, MnGnt15: BOOL; MnNewRq: BOOL; MnAdCycle: BOOL; MTransport: INT[36]; MParity: BOOL; MnShared: BOOL; MnAbort: BOOL; MnHousekeepingInProgress: BOOL; MnError: BOOL; MnDV: BOOL; <> DShift: BOOL; DExecute: BOOL; DSelectAdr: INT[12]; DDataIn: BOOL; DDataOut: BOOL; <> IOData: INT[64]; p0: ProcessorBoard[MnRq0: MnRq0, MnRq1: MnRq1, MnGnt0: MnGnt0, MnGnt1: MnGnt1]; p1: ProcessorBoard[MnRq0: MnRq2, MnRq1: MnRq3, MnGnt0: MnGnt2, MnGnt1: MnGnt3]; p2: ProcessorBoard[MnRq0: MnRq4, MnRq1: MnRq5, MnGnt0: MnGnt4, MnGnt1: MnGnt5]; p3: ProcessorBoard[MnRq0: MnRq6, MnRq1: MnRq7, MnGnt0: MnGnt6, MnGnt1: MnGnt7]; m0: MemoryBoard[]; m1: MemoryBoard[]; d0: DisplayBoard[]; d1: DisplayBoard[]; d2: DisplayBoard[]; d3: DisplayBoard[]; n0: NetworkBoard[]; misc: MiscBoard[] <<>> ENDCELLTYPE <<>> <> <<>> <> <<>> <> <> <<>> <> <> <> <<>> <> <> <<>> <> <> <<>> <> <> <<>> <> <> <<>> <> <> <<>> <> <> <<>> <<]>>