PORTS [
180 - (36+47+5+55+16) => 21
Timing and housekeeping interface (36)
PhA, nPhA, PhB, nPhB<BOOL,
Vdd, Gnd<BOOL,
PadVdd, PadGnd<BOOL,
Main memory interface (47)
MHold, MnReset<BOOL,
MnRq>BOOL,
MnGnt<BOOL,
MnNewRq>BOOL, -- Tristate
MnAdCycle=BOOL,
MTransport=INT[36],
MParity=BOOL,
MnShared=BOOL,
MnAbort>BOOL, -- Tristate
MnHousekeepingInProgress=BOOL,
MnError>BOOL, -- Tristate
MnDV=BOOL,
Serial debugging interface (5)
DShift<BOOL,
DExecute<BOOL,
DnSelect<BOOL,
DDataIn<BOOL,
DDataOut>BOOL, -- Tristate
Internal M bus (55)
IMnMRq0, IMnMRq1, IMnMRq2, IMnMRq3<BOOL,
IMnRq0, IMnRq1, IMnRq2, IMnRq3<BOOL,
IMnGnt0, IMnGnt1, IMnGnt2, IMnGnt3>BOOL,
IMnNewRq=BOOL,
IMnAdCycle=BOOL,
IMTransport=INT[36],
IMParity=BOOL,
IMnShared=BOOL,
IMnAbort=BOOL,
IMnHousekeepingInProgress=BOOL,
IMnError>BOOL, -- Tristate
IMnDV=BOOL,
RAM control (16)
RAddress=INT[14],
RnCS>BOOL,
RnWE>BOOL
]