CIRCUIT[Lambda _ 1, TDegC _ 25] = { pbus, Vdd: Node; euAdrs, neuAdrs, neuDataOut, euDataOut, phB, phA, nphA, euDataIn: Node; scDataOut, scDataIn, scAdrsLatchIn, scAdrsLatchOut, nscAdrs, camBit, n1, pullDownIn, internalMatch, nmatch, match, nArrayMatch: Node; ! ///DATools/SignalGenerators ! ///DATools/BSIM ! CacheUtilities.thy powerSupply: voltage[Vdd, Gnd] = 5.0; ?: RectWave[phA | period _ 100ns, tDelay _ 10ns, tRise _ 5ns, width _ 50ns, tFall _ 5ns]; ?: RectWave[phB | period _ 100ns, tDelay _ 60ns, tRise _ 5ns, width _ 50ns, tFall _ 5ns]; ?: RectWave[euAdrs | period _ 100ns, tDelay _ 5ns, tRise _ 5ns, width _ 95ns, tFall _ 5ns]; pbusLoad: capacitor[pbus, Gnd] = 20.0pF; phANot: Not[phA, nphA | wp _ 32, wn _ 16]; euInLoad: capacitor[euDataIn, Gnd] = 1.0pF; euDataOutLoad: capacitor[euDataIn, Gnd] = 0.01pF; euNot1: Not[euAdrs, neuAdrs | wp _ 32, wn _ 16]; euPassGate: PassGate[neuAdrs, neuDataOut, phA, nphA | w _ 16]; euNot2: Not[neuDataOut, euDataOut | wp _ 32, wn _ 16]; euTstPad: PBusIOTriStatePad[euDataOut, phA, euDataIn, pbus]; ?: Voltage[scDataOut, Gnd] = 0.0V; scTstPad: PBusIOTriStatePad[scDataOut, phB, scDataIn, pbus]; scPassGate: PassGate[scDataIn, scAdrsLatchIn, phA, nphA | w _ 16]; scAdrsLatch: Storage[scAdrsLatchIn, scAdrsLatchOut]; scNot1: Not[scAdrsLatchIn, nscAdrs | wp _ 32, wn _ 16]; scNot2: Not[nscAdrs, camBit | wp _ 128, wn _ 64]; camBitCap1: capacitor[camBit, Gnd] = 3.5pF; camBitResistor: resistor[camBit, n1] = 0.078K; camBitCap2: capacitor[n1, Gnd] = 3.5pF; Qxor: ETran[Vdd, camBit, pullDownIn | W _ 4]; Qpd: ETran[pullDownIn, Gnd, internalMatch | W _ 32]; internalMatchCap: capacitor[internalMatch, Gnd] = 2.0pF; nArrayMatchCap: capacitor[nArrayMatch, Gnd] = 2.0pF; QinternalMatchPrech: CTran[phA, Vdd, internalMatch | W _ 64]; Qweakpd: ETran[nphA, Gnd, internalMatch | L _ 4, W _ 4]; Qpu: CTran[nphA, Vdd, internalMatch | W _ 8]; matchNot1: Not[internalMatch, nmatch | wp _ 8, wn _ 4]; matchNot2: Not[nmatch, match | wp _ 16, wn _ 8]; Qarraypd: ETran[match, Gnd, nArrayMatch | W _ 32]; Qarraypu: CTran[Gnd, Vdd, nArrayMatch | W _ 32]; }; PLOT["Cache MisMatch (2 microns, 25 C)", :1ns, -1, 6, powerSupply^: -1mA, euAdrs, pbus, scAdrsLatchIn, scAdrsLatchOut, camBit, pullDownIn, internalMatch, match, nArrayMatch, phA]; RUN[tMax _ 60ns]; €SCTiming-Match.thy Created: Pradeep Sindhu March 18, 1986 2:40:01 pm PST Pradeep Sindhu March 27, 1986 10:36:32 pm PST Assume beginning of phA is at t=10ns. Κn˜šœ™Icode™5K™-—J™šΟkœ˜#J˜Jšœ˜JšœG˜GJšœ…˜…J˜J˜Jšœ˜J˜J˜Jšœ%˜%J˜J™%JšœY˜YJšœY˜YJšœ[˜[Jšœ(˜(Jšœ*˜*J˜J˜Jšœ+˜+Jšœ1˜1J˜Jšœ0˜0Jšœ>˜>Jšœ6˜6Jšœ<˜