CIRCUIT[Lambda _ 1, TDegC _ 25] = { in, int, out, clk, nclk, Vdd: Node; ! ///DATools/SignalGenerators ! ///DATools/BSIM ! CacheUtilities.thy powerSupply: voltage[Vdd, Gnd] = 5.0; PassTran: Circuit[i, o, clk, nclk | w] = { Qen: ETran[clk, i, o | W _ w]; }; Storage: Circuit[i, o | lff _ 2, wff _ 4, lfb _ 6, wfb _ 3, wen _ 12, sdExtend _ 6] = { FF: Not[i, o | lp _ lff, wp _ wff, ln _ lff, wn _ 4*wff, sdExtend _ sdExtend]; FB: Not[o, i | lp _ lfb, wp _ wfb, ln _ lfb, wn _ wfb, sdExtend _ sdExtend]; }; ?: RectWave[clk | period _ 20ns, tDelay _ 0ns, tRise _ 5ns, width _ 15ns, tFall _ 5ns]; ?: RectWave[nclk | period _ 20ns, tDelay _ 0ns, tRise _ 5ns, width _ 15ns, tFall _ 5ns, OnLevel _ 0V, OffLevel _ 5V]; ?: RectWave[in | period _ 100ns, tDelay _ 15ns, tRise _ 2ns, width _ 50ns, tFall _ 2ns]; ?: Capacitor[out, Gnd] = 0.01pF; ?: Capacitor[int, Gnd] = 0.001pF; p: PassTran[in, int, clk, nclk | w _ 32]; g: Storage[int, out | lfb _ 12]; }; PLOT["Latch with npass=32/2, ff=4/2;4/2, fb=3/6;3/6 (2 microns, 25 C)", :1ns, -1, 6, in, int, out, clk]; RUN[tMax _ 40ns]; ˜Latch.thy Created: Pradeep Sindhu March 20, 1986 11:09:02 am PST Pradeep Sindhu March 26, 1986 4:39:31 pm PST Qpen: CTran[nclk, i, o | W _ 2*w]; Êì˜™ J™6J™,—J™šÏkœ˜#J˜Jšœ#˜#J˜J˜Jšœ˜J˜J˜Jšœ%˜%J˜šÏnœ"˜*Icodešœ˜Kšœ"™"J˜—K˜šžœP˜WJšœL˜NJšœJ˜LKšœ˜—J˜J˜JšœW˜WJšœu˜uJšœX˜XJ˜ J˜!J˜Jšœ)˜)Jšœ ˜ J˜J˜Jšœd˜hJšœ˜—J˜—…—6º