SCTiming-Match.thy
Created: Pradeep Sindhu March 18, 1986 2:40:01 pm PST
Pradeep Sindhu March 27, 1986 10:36:32 pm PST
CIRCUIT[Lambda ← 1, TDegC ← 25] = {
pbus, Vdd: Node;
euAdrs, neuAdrs, neuDataOut, euDataOut, phB, phA, nphA, euDataIn: Node;
scDataOut, scDataIn, scAdrsLatchIn, scAdrsLatchOut, nscAdrs, camBit, n1, pullDownIn, internalMatch, nmatch, match, nArrayMatch: Node;
! ///DATools/SignalGenerators
! ///DATools/BSIM
! CacheUtilities.thy
powerSupply: voltage[Vdd, Gnd] = 5.0;
Assume beginning of phA is at t=10ns.
?: RectWave[phA | period ← 100ns, tDelay ← 10ns, tRise ← 5ns, width ← 50ns, tFall ← 5ns];
?: RectWave[phB | period ← 100ns, tDelay ← 60ns, tRise ← 5ns, width ← 50ns, tFall ← 5ns];
?: RectWave[euAdrs | period ← 100ns, tDelay ← 5ns, tRise ← 5ns, width ← 95ns, tFall ← 5ns];
pbusLoad: capacitor[pbus, Gnd] = 20.0pF;
phANot: Not[phA, nphA | wp ← 32, wn ← 16];
euInLoad: capacitor[euDataIn, Gnd] = 1.0pF;
euDataOutLoad: capacitor[euDataIn, Gnd] = 0.01pF;
euNot1: Not[euAdrs, neuAdrs | wp ← 32, wn ← 16];
euPassGate: PassGate[neuAdrs, neuDataOut, phA, nphA | w ← 16];
euNot2: Not[neuDataOut, euDataOut | wp ← 32, wn ← 16];
euTstPad: PBusIOTriStatePad[euDataOut, phA, euDataIn, pbus];
?: Voltage[scDataOut, Gnd] = 0.0V;
scTstPad: PBusIOTriStatePad[scDataOut, phB, scDataIn, pbus];
scPassGate: PassGate[scDataIn, scAdrsLatchIn, phA, nphA | w ← 16];
scAdrsLatch: Storage[scAdrsLatchIn, scAdrsLatchOut];
scNot1: Not[scAdrsLatchIn, nscAdrs | wp ← 32, wn ← 16];
scNot2: Not[nscAdrs, camBit | wp ← 128, wn ← 64];
camBitCap1: capacitor[camBit, Gnd] = 3.5pF;
camBitResistor: resistor[camBit, n1] = 0.078K;
camBitCap2: capacitor[n1, Gnd] = 3.5pF;
Qxor: ETran[Vdd, camBit, pullDownIn | W ← 4];
Qpd: ETran[pullDownIn, Gnd, internalMatch | W ← 32];
internalMatchCap: capacitor[internalMatch, Gnd] = 2.0pF;
nArrayMatchCap: capacitor[nArrayMatch, Gnd] = 2.0pF;
QinternalMatchPrech: CTran[phA, Vdd, internalMatch | W ← 64];
Qweakpd: ETran[nphA, Gnd, internalMatch | L ← 4, W ← 4];
Qpu: CTran[nphA, Vdd, internalMatch | W ← 8];
matchNot1: Not[internalMatch, nmatch | wp ← 8, wn ← 4];
matchNot2: Not[nmatch, match | wp ← 16, wn ← 8];
Qarraypd: ETran[match, Gnd, nArrayMatch | W ← 32];
Qarraypu: CTran[Gnd, Vdd, nArrayMatch | W ← 32];
};
PLOT["Cache MisMatch (2 microns, 25 C)", :1ns, -1, 6, powerSupply^: -1mA, euAdrs, pbus, scAdrsLatchIn, scAdrsLatchOut, camBit, pullDownIn, internalMatch, match, nArrayMatch, phA];
RUN[tMax ← 60ns];