CIRCUIT[Lambda ← 1, TDegC ← 25] = {
in, int, out, clk, nclk, Vdd: Node;
! ///DATools/SignalGenerators
! ///DATools/BSIM
! CacheUtilities.thy
powerSupply: voltage[Vdd, Gnd] = 5.0;
PassTran: Circuit[i, o, clk, nclk | w] = {
Qen: ETran[clk, i, o | W ← w];
Qpen: CTran[nclk, i, o | W ← 2*w];
};
Storage: Circuit[i, o | lff ← 2, wff ← 4, lfb ← 6, wfb ← 3, wen ← 12, sdExtend ← 6] = {
FF: Not[i, o | lp ← lff, wp ← wff, ln ← lff, wn ← 4*wff, sdExtend ← sdExtend];
FB: Not[o, i | lp ← lfb, wp ← wfb, ln ← lfb, wn ← wfb, sdExtend ← sdExtend];
};
?: RectWave[clk | period ← 20ns, tDelay ← 0ns, tRise ← 5ns, width ← 15ns, tFall ← 5ns];
?: RectWave[nclk | period ← 20ns, tDelay ← 0ns, tRise ← 5ns, width ← 15ns, tFall ← 5ns, OnLevel ← 0V, OffLevel ← 5V];
?: RectWave[in | period ← 100ns, tDelay ← 15ns, tRise ← 2ns, width ← 50ns, tFall ← 2ns];
?: Capacitor[out, Gnd] = 0.01pF;
?: Capacitor[int, Gnd] = 0.001pF;
p: PassTran[in, int, clk, nclk | w ← 32];
g: Storage[int, out | lfb ← 12];
};
PLOT["Latch with npass=32/2, ff=4/2;4/2, fb=3/6;3/6 (2 microns, 25 C)", :1ns, -1, 6, in, int, out, clk];
RUN[tMax ← 40ns];