CacheUtilities.thy
Created: Pradeep Sindhu March 18, 1986 2:40:01 pm PST
Pradeep Sindhu March 22, 1986 6:28:29 pm PST
CTran is a P-Type transistor, ETran is an N-Type transistor.
Not: Circuit[in, out | lp ← 2, wp ← 8, ln ← 2, wn ← 4, sdExtend ← 6] = {
Qp1: CTran[in, Vdd, out | L ← lp, W ← wp, sdExtend ← sdExtend];
Qn2: ETran[in, Gnd, out | L ← ln, W ← wn, sdExtend ← sdExtend];
};
NAnd: Circuit[in1, in2, out | lp ← 2, wp ← 8, ln ← 2, wn ← 8, sdExtend ← 6] = {
n: Node;
Qp1: CTran[in1, Vdd, out | L ← lp, W ← wp, sdExtend ← sdExtend];
Qp2: CTran[in2, Vdd, out | L ← lp, W ← wp, sdExtend ← sdExtend];
Qn1: ETran[in1, n, out | L ← ln, W ← wn, sdExtend ← sdExtend];
Qn2: ETran[in2, Gnd, n | L ← ln, W ← wn, sdExtend ← sdExtend];
};
NOr: Circuit[in1, in2, out | lp ← 2, wp ← 16, ln ← 2, wn ← 4, sdExtend ← 6] = {
n: Node;
Qp1: CTran[in1, Vdd, n | L ← lp, W ← wp, sdExtend ← sdExtend];
Qp2: CTran[in2, n, out | L ← lp, W ← wp, sdExtend ← sdExtend];
Qn1: ETran[in1, Gnd, out | L ← ln, W ← wn, sdExtend ← sdExtend];
Qn2: ETran[in2, Gnd, out | L ← ln, W ← wn, sdExtend ← sdExtend];
};
Latch: Circuit[in, out, clk, nclk | lff ← 2, wff ← 4, lfb ← 6, wfb ← 3, wen ← 12, sdExtend ← 6] = {
n: Node;
Qen: ETran[clk, in, n | L ← 2, W ← wen, sdExtend ← sdExtend];
Qpen: CTran[nclk, in, n | L ← 2, W ← 2*wen, sdExtend ← sdExtend];
FF: Not[n, out | lp ← lff, wp ← wff, ln ← lff, wn ← wff, sdExtend ← sdExtend];
FB: Not[out, n | lp ← lfb, wp ← wfb, ln ← lfb, wn ← wfb, sdExtend ← sdExtend];
};
PBusIOTriStatePadIn: Circuit[enableWrite, dataIn, pad | wNotIn ← 8, wpIn ← 64, wnIn ← 32, sdExtend ← 6] = {
n1, n2, n3: Node;
R: Resistor[pad, n3] = 0.5K;
NotIn: Not[n3, n1 | wp ← 2*wNotIn, wn ← wNotIn, sdExtend ← sdExtend];
QpIn1: CTran[n1, Vdd, n6 | L ← 2, W ← wpIn, sdExtend ← sdExtend];
QpIn2: CTran[enableWrite, n6, dataIn | L ← 2, W ← wpIn, sdExtend ← sdExtend];
QnIn1: ETran[n1, Gnd, n7 | L ← 2, W ← wnIn, sdExtend ← sdExtend];
QnIn2: ETran[n2, n7, dataIn | L ← 2, W ← wnIn, sdExtend ← sdExtend];
};
PBusIOTriStatePadOut: Circuit[enableWrite, dataOut, pad | wpOut ← 300, wnOut ← 144, wNor ← 32, wNAnd ← 32, wNotOut ← 16, sdExtend ← 6] = {
n2, n4, n5, n6, n7: Node;
NAndGate: NAnd[dataOut, enableWrite, n4 | wp ← wNAnd, wn ← wNAnd, sdExtend ← sdExtend];
QpOut: CTran[n4, Vdd, pad | L ← 2, W ← wpOut, sdExtend ← sdExtend];
NotOut: Not[enableWrite, n2 | wp ← 2*wNotOut, wn ← wNotOut, sdExtend ← sdExtend];
NOrGate: NOr[dataOut, n2, n5 | wp ← 4*wNor, wn ← wNor, sdExtend ← sdExtend];
QnOut: ETran[n5, Gnd, pad | L ← 2, W ← wnOut, sdExtend ← sdExtend];
};
PBusIOTriStatePad: Circuit[dataOut, enableWrite, dataIn, pad | wpOut ← 300, wnOut ← 144, wNor ← 32, wNAnd ← 32, wNotOut ← 16, wNotIn ← 8, wpIn ← 64, wnIn ← 32, sdExtend ← 6] = {
n1, n2, n3, n4, n5, n6, n7: Node;
NAndGate: NAnd[dataOut, enableWrite, n4 | wp ← wNAnd, wn ← wNAnd, sdExtend ← sdExtend];
QpOut: CTran[n4, Vdd, pad | L ← 2, W ← wpOut, sdExtend ← sdExtend];
NotOut: Not[enableWrite, n2 | wp ← 2*wNotOut, wn ← wNotOut, sdExtend ← sdExtend];
NOrGate: NOr[dataOut, n2, n5 | wp ← 4*wNor, wn ← wNor, sdExtend ← sdExtend];
QnOut: ETran[n5, Gnd, pad | L ← 2, W ← wnOut, sdExtend ← sdExtend];
R: Resistor[pad, n3] = 0.5K;
NotIn: Not[n3, n1 | wp ← 2*wNotIn, wn ← wNotIn, sdExtend ← sdExtend];
QpIn1: CTran[n1, Vdd, n6 | L ← 2, W ← wpIn, sdExtend ← sdExtend];
QpIn2: CTran[enableWrite, n6, dataIn | L ← 2, W ← wpIn, sdExtend ← sdExtend];
QnIn1: ETran[n1, Gnd, n7 | L ← 2, W ← wnIn, sdExtend ← sdExtend];
QnIn2: ETran[n2, n7, dataIn | L ← 2, W ← wnIn, sdExtend ← sdExtend];
};
TristateBuffer: Circuit[in, out, enable, nenable | wp ← 32, wn ← 16, sdExtend ← 6] = {
np, nn: Node;
?: capacitor[nn, Gnd] = 0.01pF;
?: capacitor[np, Vdd] = 0.01pF;
Qp1: CTran[in, Vdd, np | L ← 2, W ← wp, sdExtend ← sdExtend];
Qp2: CTran[nenable, np, out | L ← 2, W ← wp, sdExtend ← sdExtend];
Qn2: ETran[enable, nn, out | L ← 2, W ← wn, sdExtend ← sdExtend];
Qn1: ETran[in, Gnd, nn | L ← 2, W ← wn, sdExtend ← sdExtend];
};
PassGate: Circuit[in, out, enable, nenable | w ← 16, sdExtend ← 6] = {
Qp: CTran[nenable, in, out | L ← 2, W ← 2*w, sdExtend ← sdExtend];
Qn: ETran[enable, in, out | L ← 2, W ← w, sdExtend ← sdExtend];
};
Storage: Circuit[in, out | lff ← 2, wff ← 4, lfb ← 6, wfb ← 3, wen ← 12, sdExtend ← 6] = {
FF: Not[in, out | lp ← lff, wp ← wff, ln ← lff, wn ← wff, sdExtend ← sdExtend];
FB: Not[out, in | lp ← lfb, wp ← wfb, ln ← lfb, wn ← wfb, sdExtend ← sdExtend];
};