3 2 1 ( 0 1 ) 1 0 | ( ( x x x x ) ( x x x x ) x ) x 3 2 1 ( 0 1 ) 1 0 | ( ( x x x x ) ( x x x x ) x ) x 3 2 1 ( 0 0 ) 0 0 | ( ( x x x x ) ( x x x x ) x ) x 3 2 1 ( 0 1 ) 0 0 | ( ( x x x x ) ( x x x x ) 1 ) x 3 2 1 ( 0 1 ) 0 0 | ( ( x x x x ) ( x x x x ) 1 ) x 3 2 1 ( 0 1 ) 0 0 | ( ( 1 0 1 1 ) ( 0 1 0 0 ) 0 ) 0 3 2 1 ( 0 1 ) 1 0 | ( ( 1 0 1 1 ) ( 0 1 0 0 ) 0 ) 0 3 2 1 ( 0 1 ) 1 0 | ( ( 1 0 1 1 ) ( 0 1 0 0 ) 0 ) 0 3 2 1 ( 0 1 ) 0 0 | ( ( 1 0 1 1 ) ( 0 1 0 0 ) 1 ) 1 3 2 1 ( 1 0 ) 0 0 | ( ( 1 0 1 1 ) ( 0 1 0 0 ) 1 ) 1 3 2 1 ( 1 1 ) 0 0 | ( ( 1 0 1 1 ) ( 0 1 0 0 ) 1 ) 1 3 2 1 ( 1 1 ) 0 0 | ( ( 1 1 1 0 ) ( 0 0 0 1 ) 0 ) 0 3 2 1 ( 1 1 ) 0 0 | ( ( 1 1 1 0 ) ( 0 0 0 1 ) 0 ) 0 3 2 1 ( 1 1 ) 0 0 | ( ( 1 1 1 0 ) ( 0 0 0 1 ) 0 ) 0 3 2 1 ( 0 0 ) 1 0 | ( ( 0 1 1 1 ) ( 1 0 0 0 ) 0 ) 0 3 2 1 ( 0 1 ) 1 0 | ( ( 1 0 1 1 ) ( 0 1 0 0 ) 0 ) 0 3 2 1 ( 0 1 ) 0 0 | ( ( 1 0 1 1 ) ( 0 1 0 0 ) 1 ) 1 3 2 1 ( 1 1 ) 0 0 | ( ( 1 0 1 1 ) ( 0 1 0 0 ) 1 ) 1 3 2 1 ( 1 0 ) 1 0 | ( ( 1 0 1 1 ) ( 0 1 0 0 ) 1 ) 1 3 2 1 ( 1 0 ) 1 0 | ( ( 1 1 0 1 ) ( 0 0 1 0 ) 0 ) 0 3 2 1 ( 1 0 ) 0 0 | ( ( 1 1 0 1 ) ( 0 0 1 0 ) 1 ) 2 A B C ( 0 0 ) 0 0 | ( ( 1 1 0 1 ) ( 0 0 1 0 ) 1 ) B A B C ( 0 1 ) 1 0 | ( ( 1 1 0 1 ) ( 0 0 1 0 ) 1 ) B A B C ( 1 1 ) 1 0 | ( ( 1 1 1 0 ) ( 0 0 0 1 ) 0 ) 0 A B C ( 1 1 ) 0 0 | ( ( 1 1 1 0 ) ( 0 0 0 1 ) 1 ) A A B C ( 1 1 ) 0 0 | ( ( 1 1 1 0 ) ( 0 0 0 1 ) 1 ) A A B F ( 0 1 ) 1 0 | ( ( 1 1 1 0 ) ( 0 0 0 1 ) 1 ) A A B F ( 0 1 ) 1 0 | ( ( 1 0 1 1 ) ( 0 1 0 0 ) 0 ) 0 A F B ( 0 1 ) 0 0 | ( ( 1 0 1 1 ) ( 0 1 0 0 ) 1 ) B F B A ( 0 1 ) 0 0 | ( ( 1 0 1 1 ) ( 0 1 0 0 ) 1 ) A 3 2 1 ( 0 0 ) 0 0 | ( ( 1 0 1 1 ) ( 0 1 0 0 ) 1 ) 1 3 2 1 ( 0 0 ) 0 0 | ( ( 0 1 1 1 ) ( 1 0 0 0 ) 0 ) 0 3 2 1 ( 0 0 ) 0 0 | ( ( x x x x ) ( x x x x ) 0 ) 0 3 2 1 ( 0 0 ) 0 0 | ( ( x x x x ) ( x x x x ) 0 ) 0 3 2 1 ( 0 0 ) 1 0 | ( ( x x x x ) ( x x x x ) 0 ) 0 3 2 1 ( 0 0 ) 1 0 | ( ( x x x x ) ( x x x x ) 0 ) 0 3 2 1 ( 0 0 ) 0 0 | ( ( x x x x ) ( x x x x ) 1 ) 0 3 2 1 ( 0 0 ) 0 0 | ( ( x x x x ) ( x x x x ) 1 ) 0 3 2 1 ( 0 0 ) 0 0 | ( ( x x x x ) ( x x x x ) 1 ) 0 3 2 1 ( 0 0 ) 0 0 | ( ( x x x x ) ( x x x x ) 0 ) 0 3 2 1 ( 0 1 ) 0 0 | ( ( x x x x ) ( x x x x ) 0 ) 0 3 2 1 ( 1 0 ) 0 0 | ( ( x x x x ) ( x x x x ) 0 ) 0 3 2 1 ( 1 1 ) 0 0 | ( ( x x x x ) ( x x x x ) 0 ) 0 3 2 1 ( 0 0 ) 0 0 | ( ( x x x x ) ( x x x x ) 0 ) 0 . ^RSMux.oracle Pradeep Sindhu July 6, 1987 3:27:01 pm PDT Paraminder Sahai July 5, 1987 4:03:05 pm PDT TEST COMPLETED February 13, 1987 [PSS] Checked again after putting together cache top level July 5, 1987 4:03:05 pm PDT Note that clock supplied to circuit is half the speed of the oracle clock, so that one "cycle" corresponds to two lines in this file. Old Signal Order is: Victim LVM LRM (RSCmd) EnRamSel | ((nDecodedCmd) (DecodedCmd) EnOut) MuxOut New Signal Order is Victim LVM LRM (RSCmd) xRdRam xWtRam | ((nDecodedCmd) (DecodedCmd) EnOut) MuxOut First, check that X's get flushed out naturally, and that the Cmd decoder works: Next, check that the right values appear at the output for different inputs Then, check the timing of the negative and positive going edges of EnOut Finally, check that EnOut sets MuxOut to 0 when not asserted ÊA˜šœ™Icode™*K™,—J˜J™&J™PJ™J™J™…J™™Jšœ!Ïeœ)™LJ™JšœT™T—J™™PJ˜6J˜6J˜J˜4J˜3J˜J˜6J˜6J˜J˜6J˜6J˜J˜6J˜3J˜J˜3J˜6J˜J˜3J˜3J˜—™KJ˜3J˜3J˜J˜3J˜3J˜J˜3J˜3J˜J˜4J˜3J˜J˜3J˜3J˜J˜3J˜3J˜J˜3J˜3J˜J˜3J˜3J˜J˜3J˜3—J˜™HJ˜3J˜3J˜J˜3J˜3J˜J˜3J˜3J˜J˜3J˜3J˜—™