[Indigo]<Dragon>SmallCache>Oracle>IOLVCam.oracle!2

IOLVCam.oracle
Paraminder Sahai July 21, 1987 11:01:32 am PDT

TEST COMPLETED July 21, 1987 11:02:08 am PDT

Note that clock supplied to circuit is half the speed of the oracle clock, so that one "cycle" corresponds to two lines in this file.

The Signal Order is:
CamSelectExt Reset CSCmd1 PCtlDrABusVB PCtlDrABusVP xRdVCam PCtlPartVMch
xWtMchVCam DeMapRply1 VAdrsInOut VPValidIn AVM AVct ClampMatch |
DrBitLinesVCam VAdrsInOut VMatch

Flush out x's from the control part:

0 0 0 0 0 0 0 0 0 ( x x x x x x x x x ) 0 0 1 0 | x ( x x x x x x x x x ) x

In the following comments Lines 0,2 and 4 refer respectively to the first, second
and third line of IOLVCam.sch:

Note that Line 0 is selected when CamSelectExt is 4, Line 2 is selected when
CamSelectExt is 2 and Line 4 is selected when CamSelectExt is 1

Read each of the three lines

Line 0

0 0 0 0 0 1 0 0 0 ( x x x x x x x x x ) 0 0 1 0 | x ( x x x x x x x x x ) x

4 0 0 0 0 1 0 0 0 ( x x x x x x x x x ) 0 0 1 0 | x ( x x x x x x x x x ) x

4 0 0 0 0 0 0 0 0 ( x x x x x x x x x ) 0 0 1 0 | x ( x x x x x x x x x ) x

4 0 0 1 1 0 0 0 0 ( x x x x x x x x x ) 0 1 1 0 | x ( 1 0 0 0 0 0 0 0 1 ) x

0 0 0 1 1 0 0 0 0 ( x x x x x x x x x ) 0 1 1 0 | x ( 1 0 0 0 0 0 0 0 1 ) x

LIne 2

0 0 0 0 0 1 0 0 0 ( x x x x x x x x x ) 0 0 1 0 | x ( x x x x x x x x x ) x

2 0 0 0 0 1 0 0 0 ( x x x x x x x x x ) 0 0 1 0 | x ( x x x x x x x x x ) x

2 0 0 0 0 0 0 0 0 ( x x x x x x x x x ) 0 0 1 0 | x ( x x x x x x x x x ) x

2 0 0 1 1 0 0 0 0 ( x x x x x x x x x ) 0 1 1 0 | x ( 1 0 0 0 1 0 0 0 1 ) x

0 0 0 1 1 0 0 0 0 ( x x x x x x x x x ) 0 1 1 0 | x ( 1 0 0 0 1 0 0 0 1 ) x

Line 4 (The bit lines connected to the N cells will read as 1 because of the precharge)

0 0 0 0 0 1 0 0 0 ( x x x x x x x x x ) 0 0 1 0 | x ( x x x x x x x x x ) x

1 0 0 0 0 1 0 0 0 ( x x x x x x x x x ) 0 0 1 0 | x ( x x x x x x x x x ) x

1 0 0 0 0 0 0 0 0 ( x x x x x x x x x ) 0 0 1 0 | x ( x x x x x x x x x ) x

1 0 0 1 1 0 0 0 0 ( x x x x x x x x x ) 0 1 1 0 | x ( 1 1 1 1 1 1 0 0 1 ) x

0 0 0 1 1 0 0 0 0 ( x x x x x x x x x ) 0 1 1 0 | x ( 1 1 1 1 1 1 0 0 1 ) x

Check match circuitry

Check that ( 1 0 0 0 0 0 0 0 0 ) causes Line 0 to match

0 0 0 0 0 0 0 1 0 ( 1 0 0 0 0 0 0 0 0 ) 0 0 1 0 | x ( 1 0 0 0 0 0 0 0 0 ) x

0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) 0 0 1 0 | 1 ( 0 0 0 0 0 0 0 0 0 ) x

0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) 0 0 1 0 | 1 ( 0 0 0 0 0 0 0 0 0 ) 4

Check that ( 1 0 0 0 1 0 0 0 0 ) causes Line 2 to match

0 0 0 0 0 0 0 1 0 ( 1 0 0 0 1 0 0 0 0 ) 0 0 1 0 | x ( 1 0 0 0 1 0 0 0 0 ) x

0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) 0 0 1 0 | 1 ( 0 0 0 0 0 0 0 0 0 ) x

0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) 0 0 1 0 | 1 ( 0 0 0 0 0 0 0 0 0 ) 2

Line 4 should never match

0 0 0 0 0 0 0 1 0 ( 0 1 1 1 1 1 0 0 0 ) 0 0 1 0 | x ( 0 1 1 1 1 1 0 0 0 ) x

0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) 0 0 1 0 | 1 ( 0 0 0 0 0 0 0 0 0 ) x

0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) 0 0 1 0 | 1 ( 0 0 0 0 0 0 0 0 0 ) 0

Check that VPValid = 1 dosen't match

0 0 0 0 0 0 0 1 0 ( 1 0 0 0 0 0 0 0 0 ) 1 0 1 0 | x ( 1 0 0 0 0 0 0 0 0 ) x

0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) 1 0 1 0 | 1 ( 0 0 0 0 0 0 0 0 0 ) x

0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) 1 0 1 0 | 1 ( 0 0 0 0 0 0 0 0 0 ) 0

0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) 0 0 1 0 | 1 ( 0 0 0 0 0 0 0 0 0 ) 0

Check that Line 0 and Line 2 match when partial match is enabled

0 0 0 0 0 0 1 1 0 ( 1 0 0 1 1 1 0 0 0 ) 0 0 1 0 | x ( 1 0 0 1 1 1 0 0 0 ) x

0 0 0 0 0 0 1 0 0 ( 0 0 0 0 0 0 0 0 0 ) 0 0 1 0 | 1 ( 0 0 0 0 0 0 0 0 0 ) x

0 0 0 0 0 0 1 0 0 ( 0 0 0 0 0 0 0 0 0 ) 0 0 1 0 | 1 ( 0 0 0 0 0 0 0 0 0 ) 6

0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) 0 0 1 0 | 1 ( 0 0 0 0 0 0 0 0 0 ) 6