SCTransistorCount.tioga
Written by: Pradeep Sindhu, August 27, 1987 4:59:11 pm PDT
Last Edited by:
Pradeep Sindhu, August 18, 1986 5:25:26 pm PDT
DRAGON SMALL CACHE TRANSISTOR COUNT
DRAGON SMALL CACHE TRANSISTOR COUNT
DRAGON SMALL CACHE TRANSISTOR COUNT
DRAGON PROJECT — FOR INTERNAL XEROX USE ONLY
DRAGON PROJECT — FOR INTERNAL XEROX USE ONLY
DRAGON PROJECT — FOR INTERNAL XEROX USE ONLY
Dragon Small Cache
Transistor Count Estimate
Release as [Indigo]<Dragon>SmallCache>Documentation>SCTransistorCount.tioga, .press

© Copyright 1985 Xerox Corporation. All rights reserved.
Abstract: This document contains an estimate of the number of transistors in the cache.
XEROX   Xerox Corporation
    Palo Alto Research Center
    3333 Coyote Hill Road
    Palo Alto, California 94304



For Internal Xerox Use Only
Contents
Introduction
Appendix A: CAM Bit Line Capacitance
Appendix B: CAM Match Line Capacitance
Appendix C: RAM Bit Line Capacitance
Introduction
The calculations assume N lines in the array and F lines in the FIFO. For the IO part of the array, we assume that the number of transistors are equal to those in three lines of the memory part of the array.
Array
VCam
10 T/Cell * 64 Cells/Line * N Lines = 640 N
RCam
10 T/Cell * 64 Cells/Line * N Lines = 640 N
Flags
(10 T/Cell * 6 Cells/Line +22 T) * N Lines = 82 N
RMLatches
(8 T/Cell * 8 Cells/Line) = 64 N
Victim
(80 T/Cell * 2 Cells/Line) = 160 N
RSMux
(14 T/Cell * 2 Cells/Line) = 28 N
CSMux
(20 T/Cell * 2 Cells/Line) = 40 N
SharedOwner
(52 T/Cell * 2 Cells/Line) = 104 N
Ram
(6 T/Cell * 512 Cells/Line) = 3072 N
Total
4830N
Array Interface
VCam Interface
(84 T/Cell * 64 Cells/Line) = 5376
RCam Interface
(84 T/Cell * 64 Cells/Line) = 5376
Flags Interface
(84 T/Cell * 3 Cells/Line) = 252
Other Interfaces
The contribution due to other interfaces is ~ 1K.
Ram Interface
(54 T/Cell * 256 Cells/Line) = 13824
Total
25800
Miscellaneous Registers
Block Assembly Register
(32 T/Cell * 256 Cells/Reg) = 8192
BCycle PipeLine Registers
(32 T/Cell * 64 Cells/Reg * 5 Reg) = 10240
BWdWtPipe Registers
(32 T/Cell * 32 Cells/Reg * 2 Reg) = 2048
ABus to DBus Reg
(32 T/Cell * 32 Cells/Reg) = 1024
Processor Latches
(8 T/Cell * 32 Cells/Reg * 4 Reg) = 1024
Output Section
Rqst Buffer
(40 T/Cell * 64 Cells) = 2560
Pointers
(47 T/Cell * F Cells/Pointer * 2 Pointers) = 94F
FIFO Header
(11 T/Cell * 64 Cells/Line * F Lines) = 704F
FIFO Header Wt Interface
(32 T/Cell * 32 Cells) = 1024
FIFO Header Rd Interface
(39 T/Cell * 32 Cells) = 1248
FIFO Data
(11 T/Cell * 256 Cells/Line * F Lines) = 2816F
FIFO Data Wt Interface
(30 T/Cell * 256 Cells) = 7680
FIFO Data Rd Interface
(41 T/Cell * 256 Cells) = 10496
Control Part
All Control Parts Other than PMCode
~10 K
PMCode
~10 K
Grand Total
Array + Array Interface + Misc Regs + Output Section + Control
4830N+25800  + 22500 + (23000+3614F) + 20000
= 71300+4830N+3614F
Assuming N = 75 and F = 8, we have
Number of transistors = 71300+362000+29000 = 462300
Assuming N = 50 and F = 8, we have
Number of transistors = 71300+241500+29000 = 341800