The small cache's PInterface allows a cache to be connected to either a Dragon EU or IFU via the PBus. In typical configurations, one PBus connects the IFU to the code cache, while a second PBus connects the EU to the data cache and perhaps other devices such as a floating point unit.

This document provides the logical and electrical specifications for the PInterface. It begins in Section 2 with an overview of the PBus (the PBus is described more completely elsewhere, but we will provide relevant information directly in this document to make it easier to read). Section 3 lists the signals comprising the interface and gives the detailed characteristics of each. To avoid ambiguity, Section 4 supplies circuit diagrams for the logic actually used to send and receive each signal. Lastly, Section 5 gives the timing assumptions about the signals.

The PBus is a synchronous, low latency bus consisting of 48 wires. Of these wires, 32 comprise the multiplexed data/address path; eight define the bus command; one wire supplies the processor mode; a reject wire holds the processor for long operations; four wires are used to provide a fault indication; and two wires PhA and PhB supply the two phases of the bus clock.

Each PBus has a unique master, which implies there is no need to arbitrate for the bus. For the EU PBus the master is the EU; for the IFU PBus it is the IFU. All other devices on the bus are slaves—that is, they do not initiate operations. Slaves are designed in such a way that there is exactly one slave that will respond to a given operation. This means we cannot have conflicts where more than one slave is driving the bus and we cannot have situations where the master initiates an operation and no one responds.

PBus operation is best described in terms of transactions. Each transaction consists of one or more bus cycles, where each cycle is one period of the two phase clock (nominally 100ns). In PhA of the first cycle of a transaction, the unique bus master (either EU or IFU) sends the bus command and an address on the bus. All slaves receive this information, and exactly one of them decides that it is the one addressed by this transaction. For some commands (eg. store) PhB of the first cycle is used by the master to transmit 32 bits of data to the slave; for others (eg. fetch) this PhB is used by the slave to respond with 32 bits of data. If the slave is not able to complete the transaction in one cycle, then it asserts reject in PhB of the first cycle. This holds up the processor until there is a PhB in which the slave deasserts reject. In this PhB the slave supplies 32 bits of data if called for by the transaction.

The PInterface consists of the 48 signals listed below. The description uses the following naming conventions: S[a..b) denotes a group of b-a lines that encode the bits representing the signal S; most significant bits of the signal are written leftmost; ie., S[0] is the most significant bit. A signal represented by a single wire is written without with the [) notation. All signals are assumed to follow positive logic unless they have an "n" at the beginning of the signal name. The direction of signals (input/output) are with reference to the PInterface.

This section gives the logic diagrams for sending and receiving each of the signals just described.

This section begins with the phase relationship between PhA and PhB on the one hand and the DynaBus clock which drives the cache on the other. It then gives the timing of each of the interface signals.

This appendix gives the values of PCmd for various cache commands.