Real Cam. Matches DynaBus addresses.

Virtual Cam. Matches processor addresses. The two Cams together implement the virtual to real mapping.

Contains relatively autonomous hardware for victim selection.

Contains muxes and control to drive the Cam and Ram select lines.

Contains the shared and owner bits; these are accessed using the Ram select lines.

Contains the data. Each line contains 256 bits; two lines of Ram correspond to one line of Cam.

Contains the header cycle for a reply packet.

Contains the header cycle for a request packet.

Puts the four cycles of data for an incoming packet into the proper place for storing.

Contains an address register and two bits: stale and sharedAccumulator. Used by the consistency algorithm.

Contains header cycles waiting to be sent.

Contains data cycles waiting to be sent; each entry is up to one block.

Does bus request; pulls out data from the FIFOs and dumps it onto the bus; fairly autonomous.

Real Match in one cycle; ArrayRealMatch in < 2 cycles.

Virtual Match in one cycle; ArrayVirtualMatch in < 2 cycles.

Ram Read/Ram Write in two cycles.

RCam Read in three cycles.

RCam/VCam Write in two cycles.