Signal Name Meaning
BCycle0  Indicates that header cycle is sitting at output of BCyclePipe0
BCmd0  DynaBus command at output of BCyclePipe0
BFault0  DynaBus fault bit at output of BCyclePipe0
BDataInFCBits0 DynaBus FaultCode bits at output of BCyclePipe0
BDataIn3LSB0 3 LSB of BCyclePipe0

Signal Name Meaning
RplyShared2  RplyShared bit at output of BCyclePipe2
BCmd2  DynaBus command at output of BCyclePipe2
BFault0  DynaBus fault bit at output of BCyclePipe0

Signal Name Meaning
FBTIP  FlushBlock Transaction In Progress
NonFBTIP  Non FlushBlock Transaction In Progress
BCycle1  BCycle0 delayed one clock
BCycle2  BCycle1 delayed one clock
BCycle3  BCycle2 delayed one clock
BCycle4  BCycle3 delayed one clock
BCycle5  BCycle4 delayed one clock
BCycle6  BCycle5 delayed one clock
MyBFault  Reply packet for cache has fault bit set
MyBFaultCode Fault code from reply packet
BLdPRdLatch Loads PRdLatch
SelMSW  Select MostSignificant/LeastSignificant word of incoming cycle
EnBWdWtPipe Enables first stage of BWdWtPipe; rest are derived from this
DeMapRply1 It is Cycle 1 of a DeMapRply
ClrVPV  Clears VPValid bit  

Signal Name Meaning

BCtlSelWSData Selects WSData/WdWtData to write to Ram
BCtlRamForBCWS Reserves Ram for write part of CWS (asserted only
  if the CWSRply matches)
BCtlSelBCWS Selects WSData as input to CWS comparator
BCtlWtRam  Drive Block Assembly register/word contents onto bit lines
BCtlRdRam  Load Ram Read latches
BCtlEnRamSel Enable Ram select line
BCtlSelWdData Select Word/Block data to be written to the Ram
BCtlLdFIFO  Load FIFO with contents of RamRdLatch
BCtlSelRRdLatch Used to compute select for WdWtDataMux

Signal Name Meaning
Reset  Reset chip
Clock  DynaBus clock
nClock  inverse of DynaBus clock

Signal Name Meaning
IdMatch0  Indicates whether incoming packet's Id=MyId

Signal Name Meaning
SetReschedule Generates reschedule signal for processor

Signal Name Meaning
CWSEq  Indicates that the two inputs to the CWS comparator are equal
PCmd  Processor command
PByteSel  Processor Byte Select
PAdrs->PAdrs3LSB Low 3 bits of processor address

Signal Name Meaning
PCycle0  Indicates cycle0 of processor access
PCycle1  Indicates cycle1 of processor access
PCycle2  Indicates cycle2 of processor access
DrPBus  Drives cache data onto PBus
LdPRdLatch  Loads PRdLatch latch
DrPAdrs  Drives PAdrs onto ABus
LdPAdrs  Loads PAdrs latch
LdPWtLatch  Loads PWtLatch latch
*PReject  PBus Reject signal
*PFault  PBus Fault signal
*PReschedule PBus Reschedule signal
xSelRRdLatch Selects RRdLatch/PWtLatch as source for WdWtDataMux

Signal Name Meaning
PCtlFault  Cache detected fault
PCtlSelBFC  Selects BFaultCode/CacheFaultCode for processor
PCtlSelRRdLatch Selects RRdLatch/PWtLatch for BufData
PCtlSelRplyData Selects RplyData/WdRdData for PRdLatch
PCtlLdSnooper Loads address register in Snooper
PCtlWtMchVCam Loads VCamWtReg and drives it onto bitlines
PCtlPartVMch Make the match (if any) be a partial one
PCtlRdVCam  Loads VCamRdLatch with value on bitlines
PCtlABusCmd Selects source to drive onto ABus
PCtlFrzVictim Prevent victim pointer from moving
PCtlShftVictim Move victim to next line (only if not frozen)
PCtlLdUse  Enable loading of use bit from VMatch
PCtlSetFBTIP Sets FBTIP state bit
PCtlSetNonFBTIP Sets NonFBTIP state bit
PCtlReleaseP  Signals that it is ok for processor to proceed
PCtlWtRam  Write Ram
PCtlRdRam  Read Ram
PCtlEnRamSel Enable Ram select line
PCtlRSCmd  Selects 0|LRM|LVM|Victim as output of RSMux
PCtlSetSnooperValid Sets valid bit in Snooper
PCtlRdRCam Loads RCam read latch
PCtlWtMchRCam Loads RCamWtReg and drives it onto bitlines
PCtlEnCamSel Enables Cam select line
PCtlEnCamSelExt Connects CamSelectLineExt to CamSelectLine
PCtlCSCmd  Selects 0|LRM|LVM|Victim as output of CSMux
PCtlBusy  Indicates PCtl is busy
PCtlLdRBufDataMSW Loads most significant word of request buffer data
PCtlLdRBufDataLSW Loads least significant word of request buffer data
PCtlLdRBufHd Loads header part of request buffer data
PCtlLdFIFO  Loads FIFO from output of Ram

Signal Name Meaning
PCmd  Processor Command (3 bits only)
AVM  ArrayVirtualMatch
FBTIP  FlushBlock in progress
FBTIP  Non FlushBlock in progress
RamForP  PSide can use Ram

Signal Name Meaning
RamForP  Indicates its ok for processor to use Ram
EarlyRamForP Indicates its ok for processor to use Ram (one cycle before RamForP)
PWtInProg  Indicates processor write is in progress
xWtRam  Drives selected bits of data onto bitlines
xRdRam  Loads RamRdLatch
xEnRamSel  Enables Ram Select Line
xByteSel  Selects one or more bytes (in a word) to be written
xWdAdrs  Low 3 bits of address (thus address of word in block)
xSelWdData  Selects word data path for reading/writing Ram
xRSCmd  Selects 0|LRM|LVM|Victim as output of RSMux

Signal Name Meaning
LdRRdLatch  Load Ram RdLatch

Signal Name Meaning

ARM  Indicates at least one line in the real cam matched

Signal Name Meaning
RdRCam  Loads RCamRdLatch with value on bitlines
WtMchRCam Loads RCamWtReg and drives it onto bitlines
EnCamSel  Enables Cam Select Line
*EnCamSelExt Connects CamSelectLineExt to CamSelectLine
*PartRMch  Make the match (if any) be a partial one
CSCmd  Selects 0|LRM|LVM|Victim as output of CSMux

Signal Name Meaning

SnooperMatch2 Match signal from Snooper

Signal Name Meaning
BOwner  Pulls DynaBus owner line
BShared  Pulls DynaBus shared line
SetSh  Sets shared bit for selected line
ClrSh  Clears shared bit for selected line
RplyStale  Indicates that RBRply packet is stale

Signal Name Meaning
AOw  Array Owner bit
ASh  Array Shared bit

Signal Name Meaning

AVM  Indicates at least one line in the virtual cam matched

Signal Name Meaning

nCIn  ~CarryIn signal for victim
nCOut  ~CarryOut signal for victim