Dragon:
CEDAR
DEFINITIONS =
BEGIN
-- Dragon -- Word: TYPE = LONG CARDINAL;
HexNibble: TYPE = [0..16); -- forces hexadecimal ViewRec
HexByte: TYPE = Byte; -- forces hexadecimal ViewRec
HexWord: TYPE = Word; -- forces hexadecimal ViewRec
Byte: TYPE = [0..256);
Opcode: TYPE = HexByte;
EURegisterIndex: TYPE = [0..256);
SLRange: TYPE = EURegisterIndex[0..128);
Phase: TYPE = MACHINE DEPENDENT {a(0), b(1)};
Cycle: TYPE = NAT;
UndefinedValue: Dragon.HexWord = 01234567H;
ALUOps:
TYPE =
MACHINE
DEPENDENT {
Or(0), And(1), VAdd2(2), BndChk(3),
SAdd(4), SSub(5), LAdd(6), LSub(7),
Xor(8), res9(9), FOP(10), res11(11),
VAdd(12), VSub(13), UAdd(14), USub(15) };
aluOpSig: ALUOps = LOOPHOLE[15];
CondSelects:
TYPE =
MACHINE
DEPENDENT {
False(DragOpsCross.TrapIndex[ALUCondFalse].ORD MOD 16),
EZ(DragOpsCross.TrapIndex[ALUCondEZ].ORD MOD 16),
LZ(DragOpsCross.TrapIndex[ALUCondLZ].ORD MOD 16),
LE(DragOpsCross.TrapIndex[ALUCondLE].ORD MOD 16),
AddressCheckFault(DragOpsCross.TrapIndex[AddressCheckFault].ORD MOD 16),
NE(DragOpsCross.TrapIndex[ALUCondNE].ORD MOD 16),
GE(DragOpsCross.TrapIndex[ALUCondGE].ORD MOD 16),
GZ(DragOpsCross.TrapIndex[ALUCondGZ].ORD MOD 16),
OvFl(DragOpsCross.TrapIndex[ALUCondOver].ORD MOD 16),
BC(DragOpsCross.TrapIndex[ALUCondBC].ORD MOD 16),
IL(DragOpsCross.TrapIndex[ALUCondIL].ORD MOD 16),
res11(DragOpsCross.TrapIndex[ALUCondDO].ORD MOD 16),
res12(DragOpsCross.TrapIndex[ALUCondNotOver].ORD MOD 16),
NotBC(DragOpsCross.TrapIndex[ALUCondNB].ORD MOD 16),
NotIL(DragOpsCross.TrapIndex[ALUCondNI].ORD MOD 16),
ModeFault(DragOpsCross.TrapIndex[ModeFault].ORD MOD 16)
};
ALULeftSources: TYPE = MACHINE DEPENDENT {aBus(0), rBus(1), cBus(2), reserve3(3)};
ALURightSources:
TYPE =
MACHINE
DEPENDENT
{bBus(0), rBus(1), cBus(2), kBus(3), fCtlReg(4), reserve5(5), reserve6(6), reserve7(7)};
Store2ASources: TYPE = MACHINE DEPENDENT {bBus(0), rBus(1), cBus(2), reserve3(3)};
rd: [0..256) = 0;
wrt: [0..256) = 1;
addrCheck: [0..256) = 2;
kernelOnly: [0..256) = 4;
deviceMult: CARDINAL = 16;
cache: [0..256) = 1*deviceMult;
hold: [0..256) = kernelOnly;
io: [0..256) = 8;
au: [0..256) = 2*deviceMult;
fn: [0..256) = 8;
auLt: [0..256) = au+0;
auLtx: [0..256) = au+16;
auRt: [0..256) = au+32;
auRtx: [0..256) = au+48;
auMF: [0..256) = au+64;
auLtRt: [0..256) = au+80;
auRsLt: [0..256) = au+96;
auRsRt: [0..256) = au+108;
PBusCommands:
TYPE =
MACHINE
DEPENDENT {
NoOp(0),
Fetch(cache+rd), Store(cache+addrCheck+wrt),
FetchHold(cache+hold+rd), StoreHold(cache+hold+wrt),
IOFetch(cache+io+addrCheck+rd), IOStore(cache+io+addrCheck+wrt),
IOFetchHold(cache+io+hold+rd), IOStoreHold(cache+io+hold+wrt),
AUFetchLt(auLt+rd), AUStoreLt(auLt+wrt),
AUFetchLtFn(auLt+fn+rd), AUStoreLtFn(auLt+fn+wrt),
AUFetchLtx(auLtx+rd), AUStoreLtx(auLtx+wrt),
AUFetchLtxFn(auLtx+fn+rd),
AUFetchRt(auRt+rd), AUStoreRt(auRt+wrt),
AUFetchRtFn(auRt+fn+rd), AUStoreRtFn(auRt+fn+wrt),
AUFetchRtx(auRtx+rd), AUStoreRtx(auRtx+wrt),
AUFetchRtxFn(auRtx+fn+rd),
AUFetchMF(auMF+rd), AUStoreMF(auMF+wrt),
AUFetchMFFn(auMF+fn+rd), AUStoreMFFn(auMF+fn+wrt),
AUStoreLtRt(auLtRt+wrt),
AUFetchRslt(auRsLt+rd), AUXferToLtx(auRsLt+wrt),
AUFetchRsltFn(auRsLt+fn+rd), AUXferToLtxFn(auRsLt+fn+wrt),
AUFetchRsltx(auRsRt+rd), AUXferToRtx(auRsRt+wrt),
AUFetchRsltxFn(auRsRt+fn+rd), AUXferToRtxFn(auRsRt+fn+wrt),
Last(377B)
};
PBusFaults:
TYPE =
MACHINE
DEPENDENT {
none(0),
page(8+(DragOpsCross.TrapIndex[EUPageFault].ORD MOD 8)),
write(8+(DragOpsCross.TrapIndex[EUWriteFault].ORD MOD 8)),
arithmetic(8+(DragOpsCross.TrapIndex[AUFault].ORD MOD 8))
};
MBusCommands: TYPE = MACHINE DEPENDENT {DataTransport(0), ReadQuad(1), WriteQuad(2), WriteSingle(3), ChangeFlags(4), IORead(5), IOReadDone(6), IOWrite(7), IOWriteDone(8), Reserve9(9), Reserve10(10), Reserve11(11), Reserve12(12), Reserve13(13), Reserve14(14), NoOp(15)};
Position of a microinstruction's a, b, and c register addresses on the KBus between the IFU and EU during its clock phases 1B, 1B, and 3B, respectively.
aRegKBusPos: [0..32) = 0; -- high-order 8 bits of KBus
bRegKBusPos: [0..32) = 8;
cRegKBusPos: [0..32) = 16;
OpName: PUBLIC READONLY ARRAY Dragon.Opcode OF Rope.ROPE;
OpLength: PROC [ op: Opcode ] RETURNS [ length: [0..5] ];
Assert:
PROC [ condition:
BOOL, message: Rope.
ROPE ←
NIL ];
AssertionFailed: SIGNAL [ message: Rope.ROPE ];
Count: PROC [ a, b, c, d, e, f, g, h, i, j: BOOL ← FALSE ] RETURNS [ NAT ];
OneOf: PROC [ a, b, c, d, e, f, g, h, i, j: BOOL ← FALSE ] RETURNS [ BOOL ];
MoreThanOneOf: PROC [ a, b, c, d, e, f, g, h, i, j: BOOL ← FALSE ] RETURNS [ BOOL ];
LTD, LongToDouble: PROC[word: Dragon.HexWord] RETURNS[BitOps.BitDWord];
LFD, LongFromDouble: PROC[bdw: BitOps.BitDWord] RETURNS[Dragon.HexWord];
PRtoByte: PROC[pr:DragOpsCross.ProcessorRegister] RETURNS [byte:Dragon.HexByte];
BytetoPR: PROC[byte:Dragon.HexByte] RETURNS [pr:DragOpsCross.ProcessorRegister];
END.