Flip Flop Section
CellType : TYPE = Core.CellType;
CellTypes: TYPE = LIST OF Core.CellType;
Level: TYPE = Ports.Level;
Properties : TYPE = Core.Properties;
ROPE: TYPE = Core.ROPE;
Wire: TYPE = Core.Wire;
Wires: TYPE = Core.Wires;
PA: TYPE = CoreCreate.PA;
WR: TYPE = CoreCreate.WR;
FFState: TYPE = REF FFStateRec;
FFStateRec:
TYPE =
RECORD [
prevClk: Ports.Level,
master: Ports.Level
];
Vdd, Gnd, D, Q, Clk: NAT;
MyFF:
PUBLIC
PROC []
RETURNS [ct: CellType] = {
public: Wire ← CoreCreate.WireList[LIST["Vdd", "Gnd", "D", "Q", "Clk"]];
ct ← CoreClasses.CreateUnspecified[public: public];
[] ← Rosemary.BindCellType[cellType: ct, roseClassName: myFFName];
[] ← CoreFlat.CellTypeCutLabels[ct, "Logic"];
[Vdd, Gnd, D, Q, Clk] ← Ports.PortIndexes[ct.public, "Vdd", "Gnd", "D", "Q", "Clk"];
Ports.InitPorts[ct, b, none, "Vdd"];
Ports.InitPorts[ct, b, none, "Gnd"];
Ports.InitPorts[ct, l, none, "D"];
Ports.InitPorts[ct, l, drive, "Q"];
Ports.InitPorts[ct, l, none, "Clk"];
};
MyFFInit: Rosemary.InitProc = {
--PROC [cellType: Core.CellType, p: Ports.Port, oldStateAny: REF ANY ← NIL] RETURNS [stateAny: REF ANY ← NIL]--
ffState: FFState ← IF oldStateAny=NIL THEN NEW[FFStateRec] ELSE NARROW[oldStateAny, FFState];
ffState.prevClk ← X;
ffState.master ← X;
stateAny ← ffState;
};
MyFFEval: Rosemary.EvalProc = {
--PROC [p: Ports.Port, stateAny: REF ANY]--
ffState: FFState ← NARROW[stateAny];
IF p[Clk].l = X
THEN p[Q].l ← X
ELSE {
IF p[Clk].l = L THEN ffState.master ← p[D].l;
IF ffState.prevClk=L AND p[Clk].l=H THEN p[Q].l ← ffState.master;
};
ffState.prevClk ← p[Clk].l;
};
myFFName:
ROPE = Rosemary.Register[roseClassName: "MyFF", init: MyFFInit, evalSimple: MyFFEval];