GenName:
PROC
RETURNS [name:
ROPE] = {
IF fakeName=
LAST[
NAT]
THEN {
fakeNamePrefix ← Rope.Cat[fakeNamePrefix, "@"];
fakeName ← 0;
}
ELSE fakeName ← fakeName+1;
name ← IO.PutFR["-noname-%g%g", IO.rope[fakeNamePrefix], IO.int[fakeName]];
};
CheckWire:
PROC [wire: Core.Wire] = {
node: RoseTypes.Node;
IF wire.name = NIL THEN wire.name ← GenName[];
node ← RoseCreate.LookupCellNode[cell: thisCell, name: wire.name];
IF node=NIL THEN [] ← to.class.NodeInstance[erInstance: to.instance, name: wire.name, type: SwitchTypes.bitType];
};
FOR inst: CoreRecord.CellInstanceList ←
NARROW[InstantiateCellType.data, CoreRecord.RecordCellType].instances, inst.rest
UNTIL inst=
NIL
DO
type: CoreTransistor.TransistorType ← NARROW[inst.first.type.data, CoreTransistor.Transistor].type;
typeName:
ROPE ←
SELECT type
FROM
pE => Transistors.pE.name,
nE => Transistors.nE.name,
ENDCASE => ERROR;
wireSeq: Core.WireSequence ← inst.first.actualWire.elements;
CheckWire[wireSeq[0]];
CheckWire[wireSeq[1]];
CheckWire[wireSeq[2]];
[] ← to.class.CellInstance[erInstance: to.instance, instanceName: IF inst.first.name#NIL THEN inst.first.name ELSE GenName[], typeName: typeName, interfaceNodes: IO.PutFR["gate:%g, ch1:%g, ch2:%g", IO.rope[wireSeq[0].name], IO.rope[wireSeq[1].name], IO.rope[wireSeq[2].name]]];
ENDLOOP;