processor: {PCmdA _ xFetchy; PData _ address} cache: {PRejectB _ FALSE; PFaultB _ None}ABFigure 2a. Fetch Timing, No Reject, No FaultBAprocessor: {PCmdA _ xFetchy; PData _ address} cache: {PRejectB _ FALSE; PFaultB _ None}y: { null=> no hold, Hold}x: {null => memory, IO}cache: {PRejectB _ FALSE; PFaultB _ None; PData _ data; PParityB _ parity}Figure 2b. Fetch Timing, Reject, No FaultABABw cycles(w>=0)cache: {PRejectB _ TRUE; PFaultB _ None}cache: {PRejectB _ FALSE; PFaultB _ None}cache: {PRejectB _ TRUE; PFaultB _ None}cache: {PRejectB _ FALSE; PFaultB _ None}cache: {PRejectB _ FALSE; PFaultB _ None; PData _ data; PParityB _ parity}Figure 2. Fetch Timingcache: {PRejectB _ FALSE; PFaultB _ None}cache: {PRejectB _ TRUE; PFaultB _ None}cache: {PRejectB _ FALSE; PFaultB _ None}cache: {PRejectB _ TRUE; PFaultB _ None}(w>=0)w cyclesBABABAprocessor: {PCmdA _ xFetchy; PData _ address} cache: {PRejectB _ FALSE; PFaultB _ None}Figure 2c. Fetch Timing, Reject, Faultcache: {PRejectB _ TRUE; PFaultB _ fault}úÿøÿî VtïE-ðYîäpïE ðîäïBÐðî:ïK´ð,îäïP&ðîäïR_ðî VtïRƒðYî VïY¼ðî Vï[fðî VïPJðJî:pï5{ð)îäï<%ðîäï9íðîäï@—ðîäï>^ðî«ï>‚þ$Çî9tï@-ðî9ï?ðî VïBôð(î Vï@»ð)î Vï>‚ð(î Vï