[Indigo]<Dragon>NewerCache>Documentation>CacheImpl.tioga!1

CacheImpl.tioga

Last Edited by: Barth, December 17, 1984 7:51:30 pm PST

DRAGON CACHE IMPLEMENTATION

DRAGON PROJECT — FOR INTERNAL XEROX USE ONLY

The Dragon Cache

Implementation

Release as [Indigo]<Dragon>Cache>Documentation>CacheImpl.press

Abstract: This memo describes the Dragon cache implementation. It does not describe the client's view of the cache but rather describes the cache from a designer's point of view.

XEROX Xerox Corporation
Palo Alto Research Center
3333 Coyote Hill Road
Palo Alto, California 94304

For Internal Xerox Use Only

Contents

1. Introduction

2. Cell Design

3. Power Bus Design

4. To Be Done

1. Introduction

This document describes the implementation of the Dragon cache. The specification is described in [1]. It should be thoroughly understood prior to reading this document if a designer wishes to completely understand the cache. This document may be of some use independent of the specifications for those designers interested in the design methodology.

2. Cell Design

This section describes the detailed logic and circuit design of each cell in the cache.

StaticRAMBit

This cell is the core of the design. After considerable experience with designing the RAM for earlier versions of the cache and also a dynamic RAM test fixture [2] I knew approximately what the transistor sizes should be. The resulting cell has the undesirable property of relying upon second level metal but it has no buried contacts.

3. Power Bus Design

Mumble.

4. To Be Done

Write the RAM Rosemary code, preferably for both static and dynamic cases, including the test program.

Add

References

[1] The Dragon Cache, Description and Specifications, /Indigo/Dragon/Documentation/Cache/CacheSpecs.press

[2] CrossRAM Design, /Indigo/Dragon/CrossRAM/CrossRAM.tioga

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