Imports BitOps;Open BitOps;CELLTYPE "PCtl"PORTS[Vdd, Gnd<BOOL,PhAb, PhBb<BOOL,Resetb<BOOL, nVQMatchB, nQuadSharedB<BOOL,PStoreAB, nPStoreAB>BOOL, PQSelAB>INT[4],nPageDirtyB<BOOL,SenseVMatchA>BOOL,MDoneAB, MHeldAB<BOOL,MFaultAB<EnumType["Dragon.PBusFaults"],PCmdToMAB>EnumType["Dragon.PBusCommands"],PAdr2831AB>INT[4],DriveVirtualPageAdrBA, DriveVirtualBlockAdrBA<BOOL,StartWordMachineBA<BOOL,PDataI<INT[32],DrivePDataB, DrivePDataI>BOOL,PCmdI<EnumType["Dragon.PBusCommands"],PRejectDriveHigh, PRejectDriveLow>BOOL,PFaultDrive>BOOL,PFaultI>EnumType["Dragon.PBusFaults"],PNPErrorDriveLow>BOOL,VARegSensePDataIA, LastRefRegSenseVARegB, PageDriveCAMBitsA, BlockDriveCAMBitsA>BOOL,RefMatchesLastRefReg<BOOL,PRamRegSensePDataIB, PRamRegDrivePDataIB, PRamRegSensePBitsB, PRamRegDrivePBitsB>BOOL,PRamRegParityOut<BOOL,PAdr3031AB>INT[2]]StatePCmdLatchAB: PBusCommands,RejectAB, RejectBA, ParityError, ParityErrorLatch: BOOL,IsNoOpBA: BOOL,Mask, MustBeOne: BitWord,LastQuad, ValidWordsAB, ValidWordsBA: BitWord,RequestMatchAB: BOOL,IOReferenceAB, CacheStoreReferenceAB, CacheReferenceAB, FetchReferenceAB, HoldReferenceAB, StoreReferenceAB, RunCAM: BOOLEvalSimpleIF Resetb THEN {PCmdLatchAB _ NoOp;RejectAB _ FALSE;RejectBA _ FALSE;ParityError _ FALSE;ParityErrorLatch _ FALSE;Mask _ 0;ValidWordsAB _ 0FH;};VARegSensePDataIA _ PhAb AND NOT RejectBA;LastRefRegSenseVARegB _ PhBb AND MDoneAB;IF LastRefRegSenseVARegB THEN LastQuad _ ECFW[PAdr2831AB, 4, 0, 2];RunCAM _ (NOT RejectBA) OR MDoneAB;BlockDriveCAMBitsA _ PhAb AND (DriveVirtualBlockAdrBA OR RunCAM);PageDriveCAMBitsA _ PhAb AND (DriveVirtualPageAdrBA OR RunCAM);SenseVMatchA _ PhAb AND RunCAM;IF VARegSensePDataIA THEN {adrBits: BitWord _ 0;adrBits _ IBIW[EBFD[PDataI, 32, 2], adrBits, 4, 0];adrBits _ IBIW[EBFD[PDataI, 32, 3], adrBits, 4, 1];adrBits _ IBIW[EBFD[PDataI, 32, 22], adrBits, 4, 2];adrBits _ IBIW[EBFD[PDataI, 32, 23], adrBits, 4, 3];RequestMatchAB _ WAND[Mask, adrBits]=WAND[Mask, MustBeOne];PCmdLatchAB _ PCmdI;PAdr2831AB _ MDTW[PDataI, 32, 28, 4, PAdr2831AB, 4, 0, 4];};IOReferenceAB _ PCmdLatchAB=IOFetch OR PCmdLatchAB=IOStore OR PCmdLatchAB=IOFetchHold OR PCmdLatchAB=IOStoreHold;CacheStoreReferenceAB _ PCmdLatchAB=Store OR PCmdLatchAB=StoreHold;CacheReferenceAB _ PCmdLatchAB=Fetch OR PCmdLatchAB=FetchHold OR CacheStoreReferenceAB;FetchReferenceAB _ PCmdLatchAB=Fetch OR PCmdLatchAB=FetchHold OR PCmdLatchAB=IOFetch OR PCmdLatchAB=IOFetchHold;HoldReferenceAB _ PCmdLatchAB=FetchHold OR PCmdLatchAB=StoreHold OR PCmdLatchAB=IOFetchHold OR PCmdLatchAB=IOStoreHold;StoreReferenceAB _ CacheStoreReferenceAB OR PCmdLatchAB=IOStore OR PCmdLatchAB=IOStoreHold;IF PhBb THEN ValidWordsBA _ ValidWordsAB;IF PhAb AND StartWordMachineBA THEN ValidWordsAB _ IBIW[TRUE, 0, 4, ECFW[PAdr2831AB, 4, 2, 2]];IF PhAb AND NOT StartWordMachineBA THENFOR i:[0..4) IN [0..4) DOIF EBFW[ValidWordsBA, 4, i] THEN {FOR j:[0..4) IN [1..4) DOk: [0..4) _ (i+j) MOD 4;IF NOT EBFW[ValidWordsBA, 4, k] THEN {ValidWordsAB _ IBIW[TRUE, ValidWordsBA, 4, k];GOTO Done;};ENDLOOP;GOTO Done;};REPEATDone => NULL;ENDLOOP;IF PhBb THEN {RejectBA _ NOT MDoneAB AND RequestMatchAB AND(IOReferenceAB OR (HoldReferenceAB AND NOT MHeldAB) OR(CacheReferenceAB AND(nVQMatchB OR NOT(NOT (RefMatchesLastRefReg AND ECFW[PAdr2831AB, 4, 0, 2]=LastQuad) OR EBFW[ValidWordsAB, 4, ECFW[PAdr2831AB, 4, 2, 2]]))) OR(CacheStoreReferenceAB AND(nPageDirtyB OR NOT nQuadSharedB)));IsNoOpBA _ PCmdLatchAB=NoOp;};IF PhAb THEN RejectAB _ RejectBA;PStoreAB _ CacheStoreReferenceAB;nPStoreAB _ NOT PStoreAB;PQSelAB _ IF NOT CacheReferenceAB THEN 0 ELSE SELECT ECFW[PAdr2831AB, 4, 0, 2] FROM0 => 8,1 => 4,2 => 2,3 => 1,ENDCASE => ERROR;PCmdToMAB _ IF RequestMatchAB THEN PCmdLatchAB ELSE NoOp;DrivePDataB _ PhBb AND RequestMatchAB AND FetchReferenceAB;DrivePDataI _ NOT DrivePDataB;PRejectDriveHigh _  PhBb AND RequestMatchAB AND (RejectBA OR (MDoneAB AND MFaultAB#Dragon.None));PRejectDriveLow _ PhAb;PFaultDrive _ (PhBb AND RequestMatchAB) OR PhAb;PFaultI _ IF MDoneAB AND PhBb THEN MFaultAB ELSE Dragon.None;IF PhAb THEN ParityError _ PRamRegParityOut AND NOT RejectBA AND NOT IsNoOpBA;IF PhBb AND ParityError THEN ParityErrorLatch _ TRUE;PNPErrorDriveLow _ ParityErrorLatch;PRamRegDrivePBitsB _ PhBb AND StoreReferenceAB AND (PCmdLatchAB#StoreHold OR MHeldAB);PRamRegDrivePDataIB _ PhBb AND FetchReferenceAB;PRamRegSensePBitsB _ PRamRegDrivePDataIB;PRamRegSensePDataIB _ PhBb AND StoreReferenceAB AND NOT RejectAB;PAdr3031AB _ MWTW[PAdr2831AB, 4, 2, 2, PAdr3031AB, 2, 0, 2];ENDCELLTYPE  r  CachePInterfacePCtl.roseLast edited by: Barth, July 24, 1984 2:58:28 pm PDTLast edited by: Curry, January 29, 1985 9:30:00 pm PSTTiming and housekeeping interfaceBuffered timing and housekeeping interfaceCell controlP control <=> M controlInternal processor interfacePCAMDriver interfacePRAMDriver interfaceCombinatorial signals, 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