Imports BitOps, BitSwOps, Dragon; Open BitOps, BitSwOps, Dragon; PCtl: CELL[ Vdd, GndBOOL, PQSel>INT[4], SenseVMatch>BOOL, MDoneAB, MHeldABBOOL, PCmdToMAB>EnumType["Dragon.PBusCommands"], DoShiftBA, DoExecuteBABOOL, PCmdIBOOL, PFaultDrive>BOOL, PFaultI>EnumType["Dragon.PBusFaults"], PNPErrorDriveLow>BOOL, ShiftFeedBack, nShiftFeedBack, ShiftEqual, nShiftEqual, ShiftShift, nShiftShift>BOOL, ShiftDataToPCtlBOOL, PDataIToVAReg>BOOL, ReadVAReg, nReadVAReg>BOOL, nPBitsPrecharge, MuxRight, MuxLeft, PBitsDrive, nPBitsDrive, PRamRegToPDataI, nPRamRegToPDataI, SensePBits, SensePDataI, ParityIn>BOOL, ParityOutBOOL ] State pCmdLatch: PBusCommands, pShift, npShift: BitWord, rejectA, rejectB, parityError, parityErrorLatch: BOOL, isNoOp, suppressVirtualAccess: BOOL, rejectShift, nrejectShift, parityShift, nparityShift, requestShift, nrequestShift: BOOL, loadEnable, nloadEnable, loadMustBeOne, nloadMustBeOne, readVA, nreadVA: BOOL, mask, mustBeOne: BitWord, pAdrLowShift, npAdrLowShift, pAdrHighShift, npAdrHighShift: BOOL, requestMatch: BOOL, ioReference, cacheStoreReference, cacheReference, fetchReference, storeReference, holdReference: BOOL, shiftExecute, nShiftExecute: BOOL EvalSimple Assert[NOT MoreThanOneOf[DoShiftBA, DoExecuteBA]]; IF Resetb THEN { pCmdLatch _ NoOp; rejectA _ FALSE; rejectB _ FALSE; parityError _ FALSE; parityErrorLatch _ FALSE; mask _ 0; }; PDataIToVAReg _ PhAh AND NOT rejectB; IF PDataIToVAReg THEN { adrBits: BitWord _ 0; adrBits _ IBIW[EBFD[PDataI, 32, 2], adrBits, 4, 0]; adrBits _ IBIW[EBFD[PDataI, 32, 3], adrBits, 4, 1]; adrBits _ IBIW[EBFD[PDataI, 32, 22], adrBits, 4, 2]; adrBits _ IBIW[EBFD[PDataI, 32, 23], adrBits, 4, 3]; requestMatch _ WAND[mask, adrBits]=WAND[mask, mustBeOne]; pCmdLatch _ PCmdI; PAdrHigh _ EBFD[PDataI, 32, 30]; PAdrLowToM _ EBFD[PDataI, 32, 31]; }; ioReference _ pCmdLatch=IOFetch OR pCmdLatch=IOStore OR pCmdLatch=IOFetchHold OR pCmdLatch=IOStoreHold; cacheStoreReference _ pCmdLatch=Store OR pCmdLatch=StoreHold; cacheReference _ pCmdLatch=Fetch OR pCmdLatch=FetchHold OR cacheStoreReference; fetchReference _ pCmdLatch=Fetch OR pCmdLatch=FetchHold OR pCmdLatch=IOFetch OR pCmdLatch=IOFetchHold; holdReference _ pCmdLatch=FetchHold OR pCmdLatch=StoreHold OR pCmdLatch=IOFetchHold OR pCmdLatch=IOStoreHold; storeReference _ cacheStoreReference OR pCmdLatch=IOStore OR pCmdLatch=IOStoreHold; IF PhBh THEN rejectB _ NOT MDoneAB AND requestMatch AND (ioReference OR (holdReference AND NOT MHeldAB) OR (cacheReference AND (nVirtualMatch OR NOT nMatchTIP)) OR (cacheStoreReference AND (NOT nMatchPageClean OR NOT nMatchCellShared))); IF PhAb THEN nMatchTIP _ TRUE; IF PhAh THEN rejectA _ rejectB; IF PhBh THEN isNoOp _ pCmdLatch=NoOp; PStore _ cacheStoreReference; suppressVirtualAccess _ (pCmdLatch=StoreHold AND NOT MHeldAB) OR (NOT cacheReference); PAdrLow _ NOT suppressVirtualAccess AND PAdrLowToM; nPAdrLow _ NOT suppressVirtualAccess AND NOT PAdrLowToM; PCmdToMAB _ IF requestMatch THEN pCmdLatch ELSE NoOp; PRejectDriveHigh _ PhBb AND requestMatch AND (rejectB OR (MDoneAB AND MFaultAB#None)); PRejectDriveLow _ PhAb; PFaultDrive _ (PhBb AND requestMatch) OR PhAb; PFaultI _ IF MDoneAB AND PhBb THEN MFaultAB ELSE None; ParityIn _ FALSE; IF PhAh THEN parityError _ ParityOut AND NOT rejectB AND NOT isNoOp; IF PhBh AND parityError THEN parityErrorLatch _ TRUE; PNPErrorDriveLow _ parityErrorLatch; DrivePData _ PhBh AND requestMatch AND fetchReference; DrivePDataI _ NOT DrivePData; nPBitsPrecharge _ NOT PhAb; MuxLeft _ NOT PAdrHigh OR ioReference; MuxRight _ NOT MuxLeft; PBitsDrive _ PhBh AND storeReference; nPBitsDrive _ NOT PBitsDrive; PRamRegToPDataI _ PhBh AND fetchReference; nPRamRegToPDataI _ NOT PRamRegToPDataI; SensePBits _ PRamRegToPDataI; SensePDataI _ PhBh AND storeReference AND NOT rejectA; ShiftEqual _ PhBb; nShiftEqual _ NOT ShiftEqual; ShiftFeedBack _ PhAb AND NOT (DoShiftBA OR DoExecuteBA); nShiftFeedBack _ NOT ShiftFeedBack; ShiftShift _ PhAb AND DoShiftBA; nShiftShift _ NOT ShiftShift; shiftExecute _ PhAb AND DoExecuteBA; nShiftExecute _ NOT shiftExecute; ShiftToEnable _ (shiftExecute AND loadEnable) OR Resetb; ShiftToMustBeOne _ (shiftExecute AND loadMustBeOne) OR Resetb; ReadVAReg _ shiftExecute AND readVA; nReadVAReg _ NOT ReadVAReg; ReadPRAMReg _ shiftExecute; nReadPRAMReg _ nShiftExecute; IF shiftExecute THEN { IF readVA THEN npShift _ WNOT[LOOPHOLE[pCmdLatch], 4]; IF loadEnable THEN mask _ pShift; IF loadMustBeOne THEN mustBeOne _ pShift; nrejectShift _ rejectB; nparityShift _ parityErrorLatch; nrequestShift _ requestMatch; npAdrLowShift _ PAdrLowToM; npAdrHighShift _ PAdrHigh; }; IF ShiftShift THEN { nloadEnable _ NOT ShiftDataToPCtl; nloadMustBeOne _ NOT loadEnable; npShift _ MWTW[WNOT[pShift, 4], 4, 0, 3, npShift, 4, 1, 3]; npShift _ IBIW[NOT loadMustBeOne, npShift, 4, 0]; nrejectShift _ NOT EBFW[pShift, 4, 3]; nparityShift _ NOT rejectShift; nrequestShift _ NOT parityShift; nreadVA _ NOT requestShift; npAdrLowShift _ NOT readVA; npAdrHighShift _ NOT pAdrLowShift; }; IF ShiftFeedBack THEN { nloadEnable _ NOT loadEnable; nloadMustBeOne _ NOT loadMustBeOne; npShift _ MWTW[WNOT[pShift, 4], 4, 0, 4, npShift, 4, 0, 4]; nrejectShift _ NOT rejectShift; nparityShift _ NOT parityShift; nrequestShift _ NOT requestShift; nreadVA _ NOT readVA; npAdrLowShift _ NOT pAdrLowShift; npAdrHighShift _ NOT pAdrHighShift; }; IF ShiftEqual THEN { loadEnable _ NOT nloadEnable; loadMustBeOne _ NOT nloadMustBeOne; pShift _ MWTW[WNOT[npShift, 4], 4, 0, 4, pShift, 4, 0, 4]; rejectShift _ NOT nrejectShift; parityShift _ NOT nparityShift; requestShift _ NOT nrequestShift; readVA _ NOT nreadVA; pAdrLowShift _ NOT npAdrLowShift; pAdrHighShift _ NOT npAdrHighShift; }; ShiftDataToPRAMDriver _ pAdrHighShift; ENDCELL ,CachePCtl.rose Last edited by: Barth, June 20, 1984 6:29:10 pm PDT Timing and housekeeping interface Buffered timing and housekeeping interface Cell control P control <=> M control Debug interface Internal processor interface More debug interface PCAMDriver interface PRAMDriver interface Κ˜Jšœ™Jšœ3™3J˜Jšœ!˜!Jšœ˜J˜šœΟkœ˜ J˜šœ!™!Jšœ œ˜Jšœ œ˜—J™šœ*™*Jšœ œ˜Jšœ œ˜Jšœœ˜ —J˜™ Jšœœœ˜#Jšœ œ˜—J˜šœ™Jšœœ˜Jšœ'˜'Jšœœ˜Jšœ*˜*—J˜™Jšœœ˜—J™™Jšœœ˜Jšœ˜Jšœ&˜&Jšœ"œ˜'Jšœ œ˜Jšœ&˜&Jšœœ˜—J™™JšœPœ˜UJšœœ˜Jšœœ˜—J™šœ™Jšœœ˜Jšœœ˜—J˜™Jšœ‚œ˜‡Jšœ œ˜Jšœ˜—Jšœ˜—˜˜Jšœ˜Jšœ˜Jšœ1˜6Jšœœ˜$JšœSœ˜XJšœI˜NJšœ˜Jšœ<˜AJšœœ˜Jšœa˜fJšœ˜!—˜ Icodešœœ(˜2šœœ˜Jšœ˜Jšœ œ˜Jšœ œ˜Jšœœ˜Jšœœ˜Jšœ ˜ J˜—J•StartOfExpansion[]šœ œœœ ˜%–[]šœœ˜Jšœ˜Kšœ œœ ˜3Kšœ œœ ˜3Kšœ œœ!˜4Kšœ œœ!˜4Jšœœœ˜9Jšœ˜Jšœ œ˜ Jšœ œ˜"J˜—J˜Jšœ œœœ˜gJšœ&œ˜=Jšœ!œœ˜OJšœ!œœœ˜fJšœ$œœœ˜mJšœ%œœ˜SJ˜Jš"œœ œ œœœœœ œœœœ œœœœœ˜νJšœœ œ˜Jšœœ˜Jšœœ˜%Jšœ˜Jš œ-œœ œœ˜VJšœ œœ ˜3Jšœ œœœ ˜8Jšœ œœ œ˜5J˜Jš œœœ œ œ˜WJšœ˜Jšœœœ˜.Jš œ œ œœ œ˜6J˜Jšœ œ˜Jš œœœœ œœ˜DJšœœ œœ˜5Jšœ$˜$J˜Jšœœœ˜6Jšœœ ˜J˜Jšœœ˜Jšœ œ œ ˜&Jšœ œ ˜Jšœœ˜%Jšœœ ˜Jšœœ˜*Jšœœ˜'Jšœ˜Jšœœœœ ˜6J˜Jšœ˜Jšœœ ˜Jšœœœ œ˜8Jšœœ˜#Jšœœ ˜ Jšœœ ˜Jšœœ ˜$Jšœœ˜!J˜Jšœœ œ˜8Jšœ!œœ˜>Jšœœ˜$Jšœ œ ˜Jšœ˜Jšœ˜šœœ˜Jšœœ œœ˜6Jšœ œ˜!Jšœœ˜)Jšœ˜Jšœ ˜ Jšœ˜Jšœ˜Jšœ˜J˜—J˜šœ œ˜Jšœœ˜"Jšœœ ˜ Jšœ œœ(˜;Jšœ œœ˜1Jšœœœ˜&Jšœœ ˜Jšœœ ˜ Jšœ œ˜Jšœœ˜Jšœœ˜"J˜—šœœ˜Jšœœ ˜Jšœœ˜#Jšœ œœ(˜;Jšœœ ˜Jšœœ ˜Jšœœ˜!Jšœ œ˜Jšœœ˜!Jšœœ˜#J˜—šœ œ˜Jšœ œ ˜Jšœœ˜#Jšœ œœ(˜:Jšœœ˜Jšœœ˜Jšœœ˜!Jšœ œ ˜Jšœœ˜!Jšœœ˜#J˜—Jšœ&˜&—Jš˜—J˜J˜—…—Ό ό