Directory BitOps;Imports Dragon;Open BitOps, Dragon;MDataPads: CELL[Vdd, Gnd<BOOL,PadVdd, PadGnd<BOOL,LatchBias<BOOL,MDataBA=INT[32],MParityBA=BOOL,PhAh<BOOL,MDataI=INT[32],MParityI=BOOL,MDataDrive, MDataIDrive, MDataPipeBypass, MDataPipeTransfer<BOOL]StatemPadRegAB, mPadRegBA: BitDWord,mPadRegParityAB, mPadRegParityBA: BOOLEvalSimpleAssert[NOT MoreThanOneOf[MDataPipeBypass, MDataPipeTransfer]];IF PhAh THEN {mPadRegAB _ MDataI;mPadRegParityAB _ MParityI;};IF MDataPipeTransfer THEN {mPadRegBA _ mPadRegAB;mPadRegParityBA _ mPadRegParityAB;};IF MDataPipeBypass THEN {mPadRegBA _ MDataI;mPadRegParityBA _ MParityI;};IF MDataDrive THEN {MDataBA _ mPadRegBA;MParityBA _ mPadRegParityBA;};IF MDataIDrive THEN {MDataI _ MDataBA;MParityI _ MParityBA;};ENDCELL;MCtlPads: CELL[PhA, PhB<BOOL,Vdd, Gnd<BOOL,PadVdd, PadGnd<BOOL,LatchBias<BOOL,MCmdBA=EnumType["Dragon.MBusCommands"],MNShared=BOOL,MParityBA=BOOL,MNError>BOOL,MReadyBA<BOOL,MRq>BOOL,MNewRq=BOOL,MGnt<BOOL,ResetAB<BOOL,DHoldAB<BOOL, -- must be high before testingDShiftAB<BOOL, -- shift the shift register by 1 bit if ~DNSelectDExecuteAB<BOOL, -- interpret the content of the shift register if ~DNSelectDNSelectAB<BOOL, -- if high, hold but don't Execute or ShiftDDataInAB<BOOL,  -- sampled during each PhB that DShift is assertedDDataOutAB=BOOL,  -- changes during each PhA following a PhB that DShift is asserted, continues to be driven through the PhB following the PhA it changesPhAb, nPhAb, PhBb, nPhBb>BOOL,PhAh, PhBh>BOOL,Resetb>BOOL, DoShiftBA, DoExecuteBA, DoHoldBA>BOOL,ShiftDataToMCtlPads<BOOL,MCmdIn>EnumType["Dragon.MBusCommands"],MCmdOutBA<EnumType["Dragon.MBusCommands"],MCmdDrive<BOOL,MCmdDriveToDataTransport<BOOL,MCmdDriveToNoOp<BOOL,MNSharedSenseBA>BOOL,MNSharedDriveHigh<BOOL,MNSharedDriveLow<BOOL,MNErrorDriveLow<BOOL,MReadySense>BOOL,MRqIBA<BOOL,MNewRqIBA<BOOL,MNewRqEnableBA<BOOL,MGntSense>BOOL,ShiftDataToMRAM>BOOL,ShiftShift, nShiftShift<BOOL]StateshiftAB, shiftBA: BOOL,  -- note that these are static bits, unlike the rest of the shift registerdoHoldAB: BOOLEvalSimplePhAb _ PhA;nPhAb _ NOT PhA;PhBb _ PhB;nPhBb _ NOT PhB;IF PhBb THEN {Resetb _ ResetAB;DoHoldBA _ DHoldAB;DoShiftBA _ DShiftAB AND NOT DNSelectAB;DoExecuteBA _ DExecuteAB AND NOT DNSelectAB;shiftBA _ DDataInAB;};ShiftDataToMRAM _ shiftBA;IF ShiftShift THEN shiftAB _ ShiftDataToMCtlPads;IF NOT DNSelectAB THEN DDataOutAB _ shiftAB;IF PhAb THEN doHoldAB _ DoHoldBA;PhAh _ PhAb AND NOT DoHoldBA;PhBh _ PhBb AND NOT doHoldAB;MCmdIn _ MCmdBA;IF MCmdDrive THEN MCmdBA _ MCmdOutBA;IF MCmdDriveToDataTransport THEN MCmdBA _ DataTransport;IF MCmdDriveToNoOp THEN MCmdBA _ NoOp;MNSharedSenseBA _ MNShared;IF MNSharedDriveHigh THEN MNShared _ TRUE;IF MNSharedDriveLow THEN MNShared _ FALSE;IF MNErrorDriveLow THEN MNError _ FALSE;MReadySense _ MReadyBA;MRq _ MRqIBA;IF MNewRqEnableBA THEN MNewRq _ MNewRqIBA;MGntSense _ MGnt;ENDCELL  ╨  CacheMPads.roseLast edited by: Barth, May 23, 1984 5:13:28 pm PDTTiming and housekeeping interfaceMain memory interfaceBuffered timing and housekeeping interfaceInternal main memory interfaceTiming and housekeeping interfaceMain memory interfaceSerial debugging interfaceAll the following signals change during PhA and propagate during the remainder of PhA and PhB, giving an entire clock cycle for them to propagate throughout the machine.  Each user must receive them into a latch open during PhB.  The effects of changes are intended to happen throughout the following PhA, PhB pair.Buffered timing and housekeeping interfaceDebug interfaceInternal main memory interfaceMore debug interfaceЭ╩;  Ш JЪЬЩJЪЬ2Щ2JШ JЪЬШJЪЬШJЪЬШJШ ЪЬ╧kЬШJШ ЪЬ!Щ!JЪЬ	ЭЬШJЪЬЭЬШJЪЬ
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