Imports BitOps, BitSwOps, CacheOps, Dragon; Open BitOps, BitSwOps, Dragon; CELLTYPE "MRAMDriver" PORTS[ Vdd, GndBOOL ] State MRAMReg: BitDWord, MRAMRegParity: BOOL EvalSimple Assert[NOT MoreThanOneOf[DriveMBitsA, SenseMBitsA]]; Assert[NOT MoreThanOneOf[DriveMDataIA, SenseMDataIB]]; Assert[NOT MoreThanOneOf[DrivePBitsB, SensePBitsB]]; Assert[NOT MoreThanOneOf[SenseMBitsA, SenseMDataIB, SensePBitsB]]; TRUSTED { offset: CARDINAL _ ECFW[MAdr3031BA, 2, 0, 2]; mbitd: SwitchMWord _ DESCRIPTOR[MBitsA]; nmbitd: SwitchMWord _ DESCRIPTOR[nMBitsA]; IF SenseMDataIB THEN { MRAMReg _ MDataI; MRAMRegParity _ MParityI; }; CacheOps.DriveBus[mbitd, nmbitd, DriveMBitsA OR (DriveMBitsNoMatchA AND NOT MatchRealQuadAB), offset, MRAMReg, MRAMRegParity]; IF NOT nPhBb THEN { FOR j:CARDINAL IN [0..4) DO SCDTS[BitDWordOnes, 32, 0, 32, mbitd, 132, j*32, 32, [[none, X], [drive, H]]]; SCDTS[BitDWordOnes, 32, 0, 32, nmbitd, 132, j*32, 32, [[none, X], [drive, H]]]; ENDLOOP; SCWTS[BitWordOnes, 16, 0, 4, mbitd, 132, 128, 4, [[none, X], [drive, H]]]; SCWTS[BitWordOnes, 16, 0, 4, nmbitd, 132, 128, 4, [[none, X], [drive, H]]]; }; IF SenseMBitsA THEN { FOR i:CARDINAL IN [0..32) DO MRAMReg _ IBID[EBFS[mbitd, 132, (4*i)+offset], MRAMReg, 32, i]; ENDLOOP; MRAMRegParity _ EBFS[mbitd, 132, 128+offset]; }; }; IF DriveMDataIA OR MDataDriveDelayedA THEN { MDataI _ MRAMReg; MParityI _ MRAMRegParity; }; TRUSTED { offset: CARDINAL _ ECFW[PAdr2831AB, 4, 2, 2]; pbitd: SwitchMWord _ DESCRIPTOR[PBitsB]; npbitd: SwitchMWord _ DESCRIPTOR[nPBitsB]; CacheOps.DriveBus[pbitd, npbitd, DrivePBitsB, offset, MRAMReg, MRAMRegParity]; IF SensePBitsB THEN { FOR i:CARDINAL IN [0..32) DO MRAMReg _ IBID[EBFS[pbitd, 132, (4*i)+offset], MRAMReg, 32, i]; ENDLOOP; MRAMRegParity _ EBFS[pbitd, 132, 128+offset]; }; }; MRamRegParityOut _ CacheOps.Parity32[LOOPHOLE[MRAMReg]]; IF MRAMRegParity THEN MRamRegParityOut _ NOT MRamRegParityOut; ENDCELLTYPE FCacheMInterfaceMRAMDriver.rose Last edited by: Barth, July 26, 1984 5:25:41 pm PDT Last edited by: Curry, January 29, 1985 9:30:00 pm PST Timing and housekeeping interface Buffered timing and housekeeping interface RAM access P control <=> M control Internal main memory interface RAM ROM interface Control steel wool ΚY˜šœ™Jšœ3™3Jšœ6™6—J˜Jšœ+˜+Jšœ˜J˜šœ˜Jšœ˜J˜šœ!™!Jšœ Οkœ˜J˜—šœ*™*Jšœœ˜ J˜—™ Jšœœœ˜.Jšœœœ˜.J™—™Jšœ œ˜J˜—šœ™Jšœœ˜Jšœ œ˜J˜—™Jšœcœ˜hJ˜—™Jšœœ˜Jšœœ˜Jšœ œ˜Jšœ˜J˜—Jšœ˜J˜˜Jšœ˜Jšœ˜—˜ Icodešœœ*˜4Kšœœ,˜6Kšœœ*˜4Kšœœ8˜Bšœ˜ Jšœœœ˜-Jšœ œ ˜(Jšœ œ ˜*šœœ˜Jšœ˜Jšœ˜J˜—Jšœ-œœœ3˜~šœœœ˜šœœœ˜Jšœ8œ œ˜NJšœ9œ œ˜OJšœ˜—Jšœ4œ œ˜JJšœ5œ œ˜KJ˜—šœ œ˜šœœœ ˜Jšœ œœ,˜?Jšœ˜—Jšœœ˜-J˜—J˜—šœœœ˜,Jšœ˜Jšœ˜J˜—šœ˜ Jšœœœ˜-Jšœ œ ˜(Jšœ œ ˜*JšœN˜Nšœ œ˜šœœœ ˜Jšœ œœ,˜?Jšœ˜—Jšœœ˜-J˜—J˜—Jšœ%œ ˜8Jšœœœ˜>—Jš ˜ ——…—ά {