DIRECTORY RoseTypes, RoseCreate, BitOps, BitSwOps, CacheOps, Dragon, SwitchTypes; CacheMInterfaceMRAMDriver: CEDAR PROGRAM IMPORTS RoseCreate, BitOps, BitSwOps, CacheOps, Dragon = BEGIN OPEN RoseTypes, BitOps, BitSwOps, Dragon; RegisterCells: PROC = BEGIN [] _ RoseCreate.RegisterCellType[name: "MRAMDriver", expandProc: NIL, ioCreator: CreateMRAMDriverIO, initializer: InitializeMRAMDriver, evals: [EvalSimple: MRAMDriverEvalSimple], blackBox: NIL, stateToo: NIL, ports: CreateMRAMDriverPorts[], drivePrototype: NEW [MRAMDriverDrive]]; END; otherss: SymbolTable _ RoseCreate.GetOtherss["CacheMInterfaceMRAMDriver.pass"]; CreateMRAMDriverPorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["CacheMInterfaceMRAMDriver.MRAMDriver.rosePorts"]}; MRAMDriverIORef: TYPE = REF MRAMDriverIORec; MRAMDriverIORec: TYPE = MACHINE DEPENDENT RECORD [ fill0(0:0..14): [0..32767], Vdd(0:15..15): BOOLEAN, fill1(1:0..14): [0..32767], Gnd(1:15..15): BOOLEAN, fill2(2:0..14): [0..32767], nPhBb(2:15..15): BOOLEAN, PBitsB(3:0..2111): PACKED ARRAY [0 .. 131] OF SwitchTypes.SwitchVal, nPBitsB(135:0..2111): PACKED ARRAY [0 .. 131] OF SwitchTypes.SwitchVal, MBitsA(267:0..2111): PACKED ARRAY [0 .. 131] OF SwitchTypes.SwitchVal, nMBitsA(399:0..2111): PACKED ARRAY [0 .. 131] OF SwitchTypes.SwitchVal, fill7(531:0..11): [0..4095], PAdr2831AB(531:12..15): [0..15], MDataI(532:0..31): ARRAY [0..2) OF CARDINAL, fill9(534:0..14): [0..32767], MParityI(534:15..15): BOOLEAN, fill10(535:0..14): [0..32767], DriveMBitsA(535:15..15): BOOLEAN, fill11(536:0..14): [0..32767], DriveMBitsNoMatchA(536:15..15): BOOLEAN, fill12(537:0..14): [0..32767], SenseMBitsA(537:15..15): BOOLEAN, fill13(538:0..14): [0..32767], DriveMDataIA(538:15..15): BOOLEAN, fill14(539:0..14): [0..32767], SenseMDataIB(539:15..15): BOOLEAN, fill15(540:0..14): [0..32767], DrivePBitsB(540:15..15): BOOLEAN, fill16(541:0..14): [0..32767], SensePBitsB(541:15..15): BOOLEAN, fill17(542:0..14): [0..32767], MatchRealQuadAB(542:15..15): BOOLEAN, fill18(543:0..14): [0..32767], MDataDriveDelayedA(543:15..15): BOOLEAN, fill19(544:0..13): [0..16383], MAdr3031BA(544:14..15): [0..3], fill20(545:0..14): [0..32767], MRamRegParityOut(545:15..15): BOOLEAN]; MRAMDriverPBitsBPortIndex: CARDINAL = 3; MRAMDriverNPBitsBPortIndex: CARDINAL = 4; MRAMDriverMBitsAPortIndex: CARDINAL = 5; MRAMDriverNMBitsAPortIndex: CARDINAL = 6; MRAMDriverDrive: TYPE = MACHINE DEPENDENT RECORD [ fill0(0:0..14): [0 .. 32768), Vdd(0:15..15): BOOLEAN, fill1(1:0..14): [0 .. 32768), Gnd(1:15..15): BOOLEAN, fill2(2:0..14): [0 .. 32768), nPhBb(2:15..15): BOOLEAN, fill3(3:0..14): [0 .. 32768), PBitsB(3:15..15): BOOLEAN, fill4(4:0..14): [0 .. 32768), nPBitsB(4:15..15): BOOLEAN, fill5(5:0..14): [0 .. 32768), MBitsA(5:15..15): BOOLEAN, fill6(6:0..14): [0 .. 32768), nMBitsA(6:15..15): BOOLEAN, fill7(7:0..14): [0 .. 32768), PAdr2831AB(7:15..15): BOOLEAN, fill8(8:0..14): [0 .. 32768), MDataI(8:15..15): BOOLEAN, fill9(9:0..14): [0 .. 32768), MParityI(9:15..15): BOOLEAN, fill10(10:0..14): [0 .. 32768), DriveMBitsA(10:15..15): BOOLEAN, fill11(11:0..14): [0 .. 32768), DriveMBitsNoMatchA(11:15..15): BOOLEAN, fill12(12:0..14): [0 .. 32768), SenseMBitsA(12:15..15): BOOLEAN, fill13(13:0..14): [0 .. 32768), DriveMDataIA(13:15..15): BOOLEAN, fill14(14:0..14): [0 .. 32768), SenseMDataIB(14:15..15): BOOLEAN, fill15(15:0..14): [0 .. 32768), DrivePBitsB(15:15..15): BOOLEAN, fill16(16:0..14): [0 .. 32768), SensePBitsB(16:15..15): BOOLEAN, fill17(17:0..14): [0 .. 32768), MatchRealQuadAB(17:15..15): BOOLEAN, fill18(18:0..14): [0 .. 32768), MDataDriveDelayedA(18:15..15): BOOLEAN, fill19(19:0..14): [0 .. 32768), MAdr3031BA(19:15..15): BOOLEAN, fill20(20:0..14): [0 .. 32768), MRamRegParityOut(20:15..15): BOOLEAN]; CreateMRAMDriverIO: PROC [cell: Cell] --IOCreator-- = { cell.realCellStuff.switchIO _ NEW [MRAMDriverIORec]; cell.realCellStuff.newIO _ NEW [MRAMDriverIORec]; cell.realCellStuff.oldIO _ NEW [MRAMDriverIORec]; }; MRAMDriverStateRef: TYPE = REF MRAMDriverStateRec; MRAMDriverStateRec: TYPE = RECORD [ MRAMReg: BitDWord, MRAMRegParity: BOOL ]; InitializeMRAMDriver: Initializer = { IF leafily THEN BEGIN state: MRAMDriverStateRef _ NEW [MRAMDriverStateRec]; cell.realCellStuff.state _ state; END; }; MRAMDriverEvalSimple: CellProc = BEGIN sw: MRAMDriverIORef _ NARROW[cell.realCellStuff.switchIO]; newIO: MRAMDriverIORef _ NARROW[cell.realCellStuff.newIO]; state: MRAMDriverStateRef _ NARROW[cell.realCellStuff.state]; BEGIN OPEN newIO, state; Assert[NOT MoreThanOneOf[DriveMBitsA, SenseMBitsA]]; Assert[NOT MoreThanOneOf[DriveMDataIA, SenseMDataIB]]; Assert[NOT MoreThanOneOf[DrivePBitsB, SensePBitsB]]; Assert[NOT MoreThanOneOf[SenseMBitsA, SenseMDataIB, SensePBitsB]]; TRUSTED { offset: CARDINAL _ ECFW[MAdr3031BA, 2, 0, 2]; mbitd: SwitchMWord _ DESCRIPTOR[MBitsA]; nmbitd: SwitchMWord _ DESCRIPTOR[nMBitsA]; IF SenseMDataIB THEN { MRAMReg _ MDataI; MRAMRegParity _ MParityI; }; CacheOps.DriveBus[mbitd, nmbitd, DriveMBitsA OR (DriveMBitsNoMatchA AND NOT MatchRealQuadAB), offset, MRAMReg, MRAMRegParity]; IF NOT nPhBb THEN { FOR j:CARDINAL IN [0..4) DO SCDTS[BitDWordOnes, 32, 0, 32, mbitd, 132, j*32, 32, [[none, X], [drive, H]]]; SCDTS[BitDWordOnes, 32, 0, 32, nmbitd, 132, j*32, 32, [[none, X], [drive, H]]]; ENDLOOP; SCWTS[BitWordOnes, 16, 0, 4, mbitd, 132, 128, 4, [[none, X], [drive, H]]]; SCWTS[BitWordOnes, 16, 0, 4, nmbitd, 132, 128, 4, [[none, X], [drive, H]]]; }; IF SenseMBitsA THEN { FOR i:CARDINAL IN [0..32) DO MRAMReg _ IBID[EBFS[mbitd, 132, (4*i)+offset], MRAMReg, 32, i]; ENDLOOP; MRAMRegParity _ EBFS[mbitd, 132, 128+offset]; }; }; IF DriveMDataIA OR MDataDriveDelayedA THEN { MDataI _ MRAMReg; MParityI _ MRAMRegParity; }; TRUSTED { offset: CARDINAL _ ECFW[PAdr2831AB, 4, 2, 2]; pbitd: SwitchMWord _ DESCRIPTOR[PBitsB]; npbitd: SwitchMWord _ DESCRIPTOR[nPBitsB]; CacheOps.DriveBus[pbitd, npbitd, DrivePBitsB, offset, MRAMReg, MRAMRegParity]; IF SensePBitsB THEN { FOR i:CARDINAL IN [0..32) DO MRAMReg _ IBID[EBFS[pbitd, 132, (4*i)+offset], MRAMReg, 32, i]; ENDLOOP; MRAMRegParity _ EBFS[pbitd, 132, 128+offset]; }; }; MRamRegParityOut _ CacheOps.Parity32[LOOPHOLE[MRAMReg]]; IF MRAMRegParity THEN MRamRegParityOut _ NOT MRamRegParityOut; END; END; RegisterCells[]; END. ΨCacheMInterfaceMRAMDriver.Mesa created by RoseTranslate from CacheMInterfaceMRAMDriver.Rose of January 29, 1985 10:14:47 pm PST for curry.pa at January 29, 1985 10:16:16 pm PST Signal Type decls port indices: ΚΉ˜Icodešœ™Kšœ‘™‘K˜K˜šΟk ˜ K˜G—K˜šΠblœœ˜(Kšœ1˜8—K˜šœ˜ K˜$—K˜šœ™K˜—K˜šΟn œœ˜Kš˜˜4Kšœ œ˜K˜AK˜*Kšœ œ œ˜K˜Kšœœ˜'—Kšœ˜—K˜OK˜KšŸœœœg˜ŠK˜Kšœœœ˜,š œœœ œœ˜2K˜Kšœœ˜K˜Kšœœ˜K˜Kšœœ˜Kšœœœ œ˜DKšœœœ œ˜GKšœœœ œ˜FKšœœœ œ˜GK˜K˜ Kšœœœœ˜,K˜Kšœœ˜K˜Kšœœ˜!K˜Kšœ œ˜(K˜Kšœœ˜!K˜Kšœœ˜"K˜Kšœœ˜"K˜Kšœœ˜!K˜Kšœœ˜!K˜Kšœœ˜%K˜Kšœ œ˜(K˜K˜K˜Kšœœ˜'—K˜šœ ™ Kšœœ˜(Kšœœ˜)Kšœœ˜(Kšœœ˜)—K˜š œœœ œœ˜2K˜Kšœœ˜K˜Kšœœ˜K˜Kšœœ˜K˜Kšœœ˜K˜Kšœœ˜K˜Kšœœ˜K˜Kšœœ˜K˜Kšœœ˜K˜Kšœœ˜K˜Kšœœ˜K˜Kšœœ˜ K˜Kšœœ˜'K˜Kšœœ˜ K˜Kšœœ˜!K˜Kšœœ˜!K˜Kšœœ˜ K˜Kšœœ˜ K˜Kšœœ˜$K˜Kšœœ˜'K˜Kšœœ˜K˜Kšœœ˜&—K˜K˜šŸœœΟc œ˜7Kšœœ˜4Kšœœ˜1Kšœœ˜1K˜—K˜Kšœœœ˜2šœœœ˜#J˜Jšœ˜K˜—K˜˜%šœ ˜Kš˜Kšœœ˜5K˜!Kšœ˜—K˜—K˜˜ Kš˜Kšœœ˜:Kšœœ˜:šœœ˜=šœœ˜Jšœœ*˜4Jšœœ,˜6Jšœœ*˜4Jšœœ8˜Bšœ˜ Jšœœœ˜-Jšœ œ ˜(Jšœ œ ˜*šœœ˜J˜J˜J˜—Jšœ-œœœ3˜~šœœœ˜šœœœ˜Jšœ8œ œ˜NJšœ9œ œ˜OJšœ˜—Jšœ4œ œ˜JJšœ5œ œ˜KJ˜—šœ œ˜šœœœ ˜Jšœ œœ,˜?Jšœ˜—Jšœœ˜-J˜—J˜—šœœœ˜,J˜J˜J˜—šœ˜ Jšœœœ˜-Jšœ œ ˜(Jšœ œ ˜*J˜Nšœ œ˜šœœœ ˜Jšœ œœ,˜?Jšœ˜—Jšœœ˜-J˜—J˜—Jšœ%œ ˜8Jšœœœ˜>—Kšœ˜—Kšœ˜—K˜K˜K˜Kšœ˜—…—dυ