Directory BitOps, Dragon;Open BitOps;CELLTYPE "MPads"PORTS[PhA, PhB<BOOL,Vdd, Gnd<BOOL,PadVdd, PadGnd<BOOL,MCmdAB=EnumType["Dragon.MBusCommands"],MDataAB=INT[32],MParityAB=BOOL,MNShared=BOOL,MNError>BOOL,MRq>BOOL,MNewRq>BOOL,MGnt<BOOL,ResetAB<BOOL,DHoldAB<BOOL, -- must be high before testingDShiftAB<BOOL, -- shift the shift register by 1 bit if ~DNSelectDExecuteAB<BOOL, -- interpret the content of the shift register if ~DNSelectDNSelectAB<BOOL, -- if high, hold but don't Execute or ShiftDDataInAB<BOOL,  -- sampled during each PhB that DShift is assertedDDataOutAB=BOOL,  -- changes during each PhA following a PhB that DShift is asserted, continues to be driven through the PhB following the PhA it changesPhAb, nPhAb, PhBb, nPhBb>BOOL,Resetb>BOOL, MCmdIn>EnumType["Dragon.MBusCommands"],MCmdOutAB<EnumType["Dragon.MBusCommands"],MCmdDriveC<BOOL,MDataI=INT[32],MParityI=BOOL,MDataDriveC<BOOL,MSharedSense>BOOL,MNSharedDriveHighC<BOOL,MNSharedDriveLowC<BOOL,MNErrorDriveLow<BOOL,MRqIBA<BOOL,MNewRqIBA<BOOL,MNewRqEnableC<BOOL,MGntSenseA>BOOL]StateMPadRegAB: BitDWord,MPadRegParityAB: BOOLEvalSimplePhAb _ PhA;nPhAb _ NOT PhA;PhBb _ PhB;nPhBb _ NOT PhB;Resetb _ ResetAB;IF MCmdDriveC THEN MCmdAB _ MCmdOutAB;MCmdIn _ MCmdAB;IF PhAb THEN {MPadRegAB _ MDataI;MPadRegParityAB _ MParityI;};IF PhBb THEN {MDataI _ MDataAB;MParityI _ MParityAB;};IF MDataDriveC THEN {MDataAB _ MPadRegAB;MParityAB _ MPadRegParityAB;};MSharedSense _ NOT MNShared;IF MNSharedDriveHighC THEN MNShared _ TRUE;IF MNSharedDriveLowC THEN MNShared _ FALSE;IF MNErrorDriveLow THEN MNError _ FALSE;MRq _ MRqIBA;IF MNewRqEnableC THEN MNewRq _ MNewRqIBA;MGntSenseA _ MGnt;ENDCELLTYPE   h  CacheMInterfaceMPads.roseLast edited by: Barth, July 2, 1984 10:16:52 am PDTLast edited by: Curry, January 29, 1985 9:30:00 pm PSTTiming and housekeeping interfaceMain memory interfaceSerial debugging interfaceAll the following signals change during PhA and propagate during the remainder of PhA and PhB, giving an entire clock cycle for them to propagate throughout the machine.  Each user must receive them into a latch open during PhB.  The effects of changes are intended to happen throughout the following PhA, PhB pair.Buffered timing and housekeeping interfaceInternal main memory interfaceÊ9  ˜ šœ™Jšœ3™3Jšœ6™6—J˜ Jšœ˜Jšœ˜J˜ šœ˜Jšœ˜J˜ šœ!™!Jšœ	Ïkœ˜Jšœ	œ˜Jšœœ˜—J™ šœ™Jšœ'˜'Jšœœ˜Jšœ
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