Library CacheMInterfaceMCAMDriver, CacheMInterfaceMRAMDriver, CacheMInterfaceMEntryCtl, CacheMInterfaceMSequencer, CacheMInterfaceMPads, CacheMInterfaceMROM; CELLTYPE "MInterface" PORTS[ PhA, PhBBOOL, MRq>BOOL, MNewRq>BOOL, MGntBOOL, Resetb>BOOL, CAMPage, nCAMPage=SWITCH[24]-(Special XPhobic), CAMBlock, nCAMBlock=SWITCH[4]-(Special XPhobic), PBitsB, nPBitsB=SWITCH[132]-(Special XPhobic), MBitsA, nMBitsA=SWITCH[132]-(Special XPhobic), nVQMatchB, nQuadSharedB=BOOL, nRQMatchA=BOOL, nPageDirtyB, nMapValidB=BOOL, nRealBlockMatchA, nVirtualBlockMatchB=BOOL, QValidA, nQValidA, QSharedA, nQSharedA, QMasterA, nQMasterA=BIT-(Special XPhobic), MQSelBA, MatchQSelBA>INT[4], nQDirtyB=INT[4], RPValidBitA, nRPValidBitA, RPDirtyBitA, nRPDirtyBitA, VPValidBitA, nVPValidBitA=BIT-(Special XPhobic), ForceAllDataSelectsBA>BOOL, CellAdrBA, nCellAdrBA>INT[7], SelOrphanAdrBA, SelMapAdrBA, SelVPBA, SelRPVictimBA, SelRPDecoderBA, SelRealDataBA, SelDecodeBA>BOOL, FinishSharedStoreAB>BOOL, SenseRMatchB, SenseVictimA, SelPageFlagsBA>BOOL, MDoneAB, MHeldAB>BOOL, MFaultAB>EnumType["Dragon.PBusFaults"], PCmdToMABBOOL, StartWordMachineBA>BOOL ] Expand MCmdIn:EnumType["Dragon.MBusCommands"]; MCmdOutAB:EnumType["Dragon.MBusCommands"]; MCmdDriveC:BOOL; MDataI:INT[32]; MParityI:BOOL; MDataDriveC:BOOL; MSharedSense:BOOL; MNSharedDriveHighC:BOOL; MNSharedDriveLowC:BOOL; MNErrorDriveLow:BOOL; MRqIBA:BOOL; MNewRqIBA:BOOL; MNewRqEnableC:BOOL; MGntSenseA:BOOL; CAMRegSenseMDataIB, ACAMRegDriveCAMBitsA, BCAMRegDriveCAMBitsAB, FormAddressBA, PageDriveMDataIA, BlockDriveMDataIA:BOOL; DriveMBitsA, DriveMBitsNoMatchA, SenseMBitsA, DriveMDataIA, SenseMDataIB, DrivePBitsB, SensePBitsB:BOOL; SuppressPSampleAB, MIsDoneAB, SetWantWSA, CheckFaultsAB, SenseSharedB, ReleaseMBusBA, ForceIdleAB, DoneAB, ForceSlaveBA, SenseReadyBA, MDataIToFaultsB, MapBitsToMDataIA, ACheckParityA, BCheckParityB, SampleRealMatchA, MCmdDriveA, MDataDriveA, DriveSharedHighA, DriveSharedLowA, MasterEnableMBusDriveAB, MCmdDriveToDataTransportAB, MCmdDriveToNoOpAB:BOOL; SetSharedA, ResetMasterA, SetRPDirtyVPValidA, FlagLatchB, SetFlagsA, IncrementVictimBA, IncrementMAdrCtrB, ZeroMAdrCtrB, SampleDirtyBitsB, DeleteDirtyBitB, VictimSelectBA, RefreshToDecoderBA, IfGrantThenGetAdrElseRefreshToDecoderBA, FetchAddressBA, DirtyBitsToMQSelBA, SamplePAdr2831B, SampleMAdr2831B, Adr2829ToMQSelBA, AddressBitsToMDataIA, VictimAddressBitsToMDataIA, SelectRPBA, SelectVPVictimOrOrphanBA, SelectRealDataBA, SelVictimOrOrphanBA, RefreshIfRefVirtualBA, SenseVictimBA:BOOL; GetAdrCmdBA:EnumType["CacheOps.PreFetchAdrCmd"]; IsCleanBA, LatchSharedBA, MasterBA, MatchRealQuadAB, MatchRealBlockAB, ContinueBA:BOOL; OneDirtyBA, SomeDirtyBA, MDataDriveDelayedA:BOOL; ROMSequenceBA:INT[7]; ROMSlaveBA:BOOL; ROMCycleBA:INT[7]; MAdr3031BA:INT[2]; MRamRegParityOut:BOOL; mCAMDriver: MCAMDriver[]; mRAMDriver: MRAMDriver[]; mEntryCtl: MEntryCtl[]; mSequencer: MSequencer[]; mPads: MPads[]; mROM: MROM[] ENDCELLTYPE CacheMInterface.rose Last edited by: Barth, July 27, 1984 5:35:07 pm PDT Last edited by: Curry, February 1, 1985 9:18:18 am PST Timing and housekeeping interface Main memory interface Serial debugging interface All the following signals change during PhA and propagate during the remainder of PhA and PhB, giving an entire clock cycle for them to propagate throughout the machine. Each user must receive them into a latch open during PhB. The effects of changes are intended to happen throughout the following PhA, PhB pair. Buffered timing and housekeeping interface CAM interface RAM access Cell control P control <=> M control Internal main memory interface CAM driver ROM interface RAM ROM interface Sequencer ROM interface Entry Control ROM interface Control steel wool ʘšœ™Jšœ3™3Jšœ6™6—J˜J˜J˜šœ˜šœ˜J˜šœ!™!Jšœ Ïkœ˜Jšœ œ˜Jšœœ˜—J™šœ™Jšœ'˜'Jšœœ˜Jšœ œ˜Jšœ œ˜Jšœœ˜ Jšœœ˜ Jšœœ˜ Jšœœ˜ —J™šœ™Jšœ»™»Jšœœ˜ JšœœÏc˜,Jšœ œž1˜@Jšœ œž;˜LJšœ œž+˜