MCtlRAMCtl: CELL[Vdd, Gnd<BOOL,LatchBias<BOOL,PhBb<BOOL,PAdrHigh<BOOL,DoHoldBA<BOOL,ShiftDataToMCtl<BOOL,ShiftEqual, nShiftEqual, ShiftFeedBack, nShiftFeedBack, ShiftShift, nShiftShift<BOOL,nMBitsPrecharge, MuxRight, MuxLeft, MBitsDrive, nMBitsDrive, MRamRegToMDataI, nMRamRegToMDataI, SenseMBits, SenseMDataI, ParityIn>BOOL,SensePBitsLeft, SensePBitsRight, DrivePBits, nDrivePBits>BOOL,MRamRegToMBits, nMRamRegToMBits>BOOL,ShiftToMBits, nShiftToMBits, MBitsToShift, nMBitsToShift>BOOL,ShiftDataToFlagCtl>BOOL,ReadEntry, WriteEntry<BOOL,ShiftExecute, nShiftExecute<BOOL,RAMMDataIToMRAMReg, RAMMBitsToMRAMReg, RAMMRAMRegToMDataI, RAMMRAMRegToMBits, RAMMRAMRegToMBitsNoOrphan, RAMPBitsToMRAMReg, RAMLeftPBitsToMRAMReg, RAMMRAMRegToPBits<BOOL,MatchRealBA, MAdrHigh<BOOL]StateshiftHighAddress, nshiftHighAddress: BOOL,MAdrCtrAB, MAdrCtrBA: CARDINALEvalSimpleIF IncrementMAdrCtrB THEN MAdrCtrBA _ (MAdrCtrAB+1) MOD 4;IF PhAb THEN {MAdrCtrAB _ MAdrCtrBA;};IF LoadMAdrCtrFromMDataIB THEN MAdrCtrBA _ ECFD[MDataI, 32, 30, 2];IF ZeroMAdrCtrB THEN MAdrCtrBA _ 0;IF LoadMAdrCtrFromPAdrB THEN MAdrCtrBA _ MWTW[PAdrAB, 4, 2, 2, MAdrCtrBA, 2, 0, 2];nMBitsPrecharge _ NOT PhBb;MuxLeft _ IF DoHoldBA THEN shiftHighAddress ELSE NOT MAdrHigh;MuxRight _ NOT MuxLeft;MRamRegToMBits _ (RAMMRAMRegToMBits OR (RAMMRAMRegToMBitsNoOrphan AND NOT MatchRealBA));nMRamRegToMBits _ NOT MRamRegToMBits;ShiftToMBits _ ShiftExecute AND WriteEntry;nShiftToMBits _ NOT ShiftToMBits;MBitsDrive _ MRamRegToMBits OR ShiftToMBits;nMBitsDrive _ NOT MBitsDrive;MRamRegToMDataI _ RAMMRAMRegToMDataI;nMRamRegToMDataI _ NOT MRamRegToMDataI;SenseMBits _ RAMMBitsToMRAMReg;SenseMDataI _ RAMMDataIToMRAMReg;ParityIn _ FALSE;SensePBitsLeft _ RAMLeftPBitsToMRAMReg OR (RAMPBitsToMRAMReg AND NOT PAdrHigh);SensePBitsRight _ RAMPBitsToMRAMReg AND PAdrHigh;DrivePBits _ RAMMRAMRegToPBits;nDrivePBits _ NOT RAMMRAMRegToPBits;MBitsToShift _ ShiftExecute AND ReadEntry;nMBitsToShift _ NOT MBitsToShift;IF ShiftShift THEN nshiftHighAddress _ NOT ShiftDataToMCtl;IF ShiftFeedBack THEN nshiftHighAddress _ NOT shiftHighAddress;IF ShiftEqual THEN shiftHighAddress _ NOT nshiftHighAddress;ShiftDataToFlagCtl _ shiftHighAddress;ENDCELL  6  CacheMCtlRAMCtl.roseLast edited by: Barth, June 21, 1984 3:47:17 pm PDTTiming and housekeeping interfaceBuffered timing and housekeeping interfaceP control <=> M controlDebug interfaceMore debug interfaceMRAMDriver interfaceStill more debug interfaceRAM control interfaceControl steel wool ‌تم  ک Jڑœ™Jڑœ3™3Jک ڑœدkœکJک ڑœ!™!Jڑœ	‌œکJڑœ
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