Imports BitOps, BitSwOps, Dragon;
Open BitOps, BitSwOps;

Cedar
numberOfQuads: INT = 4;
numberOfWords: INT = 4;
numberOfEntries: INT = 4;
quadIndex: TYPE = [0..numberOfQuads);
wordIndex: TYPE = [0..numberOfWords);
memBits: TYPE = ARRAY [0..2*numberOfWords+1) OF BitWord;
QuadState: TYPE = RECORD[
Master, nMaster: BOOL,
SharedAB, nSharedAB: BOOL,
ValidAB, nValidAB: BOOL,
Data: ARRAY BOOLEAN OF memBits,
PSelB, MSelA: BOOL
];
;

CELLTYPE "CacheEntry"
PORTS[

Vdd, Gnd<BOOL,
PhAb, PhBb<BOOL,
CAMPage, nCAMPage=SWITCH[24]-(Special XPhobic),
CAMBlock, nCAMBlock=SWITCH[4]-(Special XPhobic),

PBitsB, nPBitsB=SWITCH[132]-(Special XPhobic),
MBitsA, nMBitsA=SWITCH[132]-(Special XPhobic),

nVQMatchB, nQuadSharedB>BOOL,
QValidA, nQValidA, QSharedA, nQSharedA, QMasterA, nQMasterA=BIT-(Special XPhobic),
MQSelBA, MatchQSelBA<INT[4], nRQMatchA>BOOL, FinishSharedStoreAB<BOOL, nQDirtyB>INT[4],
PStoreAB, nPStoreAB<BOOL, PQSelAB<INT[4],
nPageDirtyB, nMapValidB>BOOL,
RPValidBitA, nRPValidBitA, RPDirtyBitA, nRPDirtyBitA, VPValidBitA, nVPValidBitA=BIT-(Special XPhobic),
ForceAllDataSelectsBA<BOOL, nRealBlockMatchA, nVirtualBlockMatchB>BOOL,
CellAdrBA, nCellAdrBA<INT[7],
SenseRMatchB, SenseVictimA, SelOrphanAdrBA, SelMapAdrBA, SelVPBA, SelRPVictimBA, SelRPDecoderBA, SelRealDataBA, SelPageFlagsBA, SelDecodeBA<BOOL,
SenseVMatchA<BOOL,

DecodeSelectOutBA>BOOL,
DecodeSelectInBA<BOOL
]

State
VPSelectAB, VBlSelectAB, RPSelectBA, RBlSelectBA, VictimSelectAB: BOOL,
VPValidAB, nVPValidAB: BOOL,
RPValidAB, nRPValidAB: BOOL,
RPDirtyAB, nRPDirtyAB: BOOL,
quadData: ARRAY quadIndex OF QuadState,
hexVirtualPage, hexRealPage, hexBlock: Dragon.HexWord,
words: ARRAY quadIndex OF ARRAY wordIndex OF Dragon.HexWord,
parity: ARRAY quadIndex OF ARRAY wordIndex OF BOOL,
VirtualPageAB, nVirtualPageAB: BitDWord,
RealPageAB, nRealPageAB: BitDWord,
BlockAB, nBlockAB: BitWord,
VSelMapAB, VSelCellAB, RSelMapBA, RSelCellBA: BOOL,
RPAccessA, BlockAccessA, VPAccessA, DataSelectA, FlagSelectA: BOOL,
thisCellAdr: BitWord
EvalSimple
oldMemBits: ARRAY quadIndex OF memBits;

RWB: PROC [access: BOOL, bus, nBus: Switch, bit, nbit: BOOL] RETURNS [newBus, nNewBus: Switch, newBit, newnBit: BOOL] = {
s: SwitchTypes.Strength _ IF access THEN drive ELSE none;
IF access THEN {
bit _ (NOT nbit) AND bus.val=H;
nbit _ (NOT bit) AND nBus.val=H;
bit _ (NOT nbit) AND bus.val=H;
};
nNewBus _ SIBISS[bit, nBus, [[none, X], [s, L]]];
newBus _ SIBISS[nbit, bus, [[none, X], [s, L]]];
newBit _ bit;
newnBit _ nbit;
};

RWW: PROC [access: BOOL, busD, nBusD: SwitchMWord, field, nfield: BitWord, fieldWidth: CARDINAL] RETURNS [newField, newnField: BitWord] = TRUSTED {
s: SwitchTypes.Strength _ IF access THEN drive ELSE none;
IF access THEN FOR i:CARDINAL IN [0..fieldWidth) DO
field _ IBIW[(NOT EBFW[nfield, fieldWidth, i]) AND busD[i].val=H, field, fieldWidth, i];
nfield _ IBIW[(NOT EBFW[field, fieldWidth, i]) AND nBusD[i].val=H, nfield, fieldWidth, i];
field _ IBIW[(NOT EBFW[nfield, fieldWidth, i]) AND busD[i].val=H, field, fieldWidth, i];
ENDLOOP;
SCWTS[field, fieldWidth, 0, fieldWidth, nBusD, fieldWidth, 0, fieldWidth, [[none, X], [s, L]]];
SCWTS[nfield, fieldWidth, 0, fieldWidth, busD, fieldWidth, 0, fieldWidth, [[none, X], [s, L]]];
newField _ field;
newnField _ nfield;
};

RWD: PROC [access: BOOL, busD, nBusD: SwitchMWord, field, nfield: BitDWord, fieldWidth: CARDINAL] RETURNS [newField, newnField: BitDWord] = TRUSTED {
s: SwitchTypes.Strength _ IF access THEN drive ELSE none;
IF access THEN FOR i:CARDINAL IN [0..fieldWidth) DO
field _ IBID[(NOT EBFD[nfield, fieldWidth, i]) AND busD[i].val=H, field, fieldWidth, i];
nfield _ IBID[(NOT EBFD[field, fieldWidth, i]) AND nBusD[i].val=H, nfield, fieldWidth, i];
field _ IBID[(NOT EBFD[nfield, fieldWidth, i]) AND busD[i].val=H, field, fieldWidth, i];
ENDLOOP;
SCDTS[field, fieldWidth, 0, fieldWidth, nBusD, fieldWidth, 0, fieldWidth, [[none, X], [s, L]]];
SCDTS[nfield, fieldWidth, 0, fieldWidth, busD, fieldWidth, 0, fieldWidth, [[none, X], [s, L]]];
newField _ field;
newnField _ nfield;
};

RWM: PROC [access: BOOL, busD, nBusD: SwitchMWord, field, nfield: BitMWord, fieldWidth: CARDINAL] = TRUSTED {
s: SwitchTypes.Strength _ IF access THEN drive ELSE none;
IF access THEN FOR i:CARDINAL IN [0..fieldWidth) DO
IBIM[(NOT EBFM[nfield, fieldWidth, i]) AND busD[i].val=H, field, fieldWidth, i];
IBIM[(NOT EBFM[field, fieldWidth, i]) AND nBusD[i].val=H, nfield, fieldWidth, i];
IBIM[(NOT EBFM[nfield, fieldWidth, i]) AND busD[i].val=H, field, fieldWidth, i];
ENDLOOP;
SCMTS[field, fieldWidth, 0, fieldWidth, nBusD, fieldWidth, 0, fieldWidth, [[none, X], [s, L]]];
SCMTS[nfield, fieldWidth, 0, fieldWidth, busD, fieldWidth, 0, fieldWidth, [[none, X], [s, L]]];
};

FOR i:quadIndex IN quadIndex DO
oldMemBits[i] _ quadData[i].Data[TRUE];
ENDLOOP;

TRUSTED {
cp: BitDWord _ CSTD[DESCRIPTOR[CAMPage], 24, 0, 24, BitDWordZero, 24, 0, 24];
ncp: BitDWord _ CSTD[DESCRIPTOR[nCAMPage], 24, 0, 24, BitDWordZero, 24, 0, 24];
cb: BitWord _ CSTW[DESCRIPTOR[CAMBlock], 4, 0, 4, 0, 4, 0, 4];
ncb: BitWord _ CSTW[DESCRIPTOR[nCAMBlock], 4, 0, 4, 0, 4, 0, 4];
IF SenseVMatchA THEN {
VPSelectAB _ DAND[ncp, VirtualPageAB]=BitDWordZero AND DAND[cp, nVirtualPageAB]=BitDWordZero;
VBlSelectAB _ WAND[ncb, BlockAB]=0 AND WAND[cb, nBlockAB]=0;
};
IF SenseRMatchB THEN {
RPSelectBA _ DAND[ncp, RealPageAB]=BitDWordZero AND DAND[cp, nRealPageAB]=BitDWordZero;
RBlSelectBA _ WAND[ncb, BlockAB]=0 AND WAND[cb, nBlockAB]=0;
};
};
VSelMapAB _ VPValidAB AND VPSelectAB;
VSelCellAB _ VSelMapAB AND VBlSelectAB;
RSelMapBA _ RPValidAB AND RPSelectBA;
RSelCellBA _ RSelMapBA AND RBlSelectBA;
IF VSelMapAB AND PhBb THEN {
nMapValidB _ FALSE;
IF RPDirtyAB THEN nPageDirtyB _ FALSE;
};
IF VSelCellAB AND PhBb THEN nVirtualBlockMatchB _ FALSE;
IF RSelCellBA AND PhAb THEN nRealBlockMatchA _ FALSE;
DecodeSelectOutBA _ CellAdrBA=thisCellAdr AND CellAdrBA=WNOT[nCellAdrBA, 7];
IF SenseVictimA THEN VictimSelectAB _ DecodeSelectInBA;
IF NOT PhAb THEN {
RPAccessA _ FALSE;
BlockAccessA _ FALSE;
VPAccessA _ FALSE;
DataSelectA _ FALSE;
FlagSelectA _ FALSE;
};
IF PhAb THEN {
IF (SelMapAdrBA AND VSelMapAB) OR (SelRPDecoderBA AND DecodeSelectOutBA) OR (SelRPVictimBA AND VictimSelectAB) THEN RPAccessA _ TRUE;
IF (SelRPDecoderBA AND DecodeSelectOutBA) OR (SelRPVictimBA AND VictimSelectAB) THEN BlockAccessA _ TRUE;
IF (SelOrphanAdrBA AND RSelCellBA) OR (SelVPBA AND DecodeSelectOutBA) THEN VPAccessA _ TRUE;
IF (SelRealDataBA AND RSelCellBA) OR (DecodeSelectOutBA AND SelDecodeBA) OR ForceAllDataSelectsBA THEN DataSelectA _ TRUE;
IF (SelPageFlagsBA AND RSelMapBA) OR DataSelectA THEN FlagSelectA _ TRUE;
};
[RPValidBitA, nRPValidBitA, RPValidAB, nRPValidAB] _ RWB[DataSelectA, RPValidBitA, nRPValidBitA, RPValidAB, nRPValidAB];
[RPDirtyBitA, nRPDirtyBitA, RPDirtyAB, nRPDirtyAB] _ RWB[FlagSelectA, RPDirtyBitA, nRPDirtyBitA, RPDirtyAB, nRPDirtyAB];
[VPValidBitA, nVPValidBitA, VPValidAB, nVPValidAB] _ RWB[FlagSelectA, VPValidBitA, nVPValidBitA, VPValidAB, nVPValidAB];
TRUSTED {
busD: SwitchMWord _ DESCRIPTOR[CAMPage];
nBusD: SwitchMWord _ DESCRIPTOR[nCAMPage];
[VirtualPageAB, nVirtualPageAB] _ RWD[VPAccessA, busD, nBusD, VirtualPageAB, nVirtualPageAB, 24];
};
TRUSTED {
busD: SwitchMWord _ DESCRIPTOR[CAMPage];
nBusD: SwitchMWord _ DESCRIPTOR[nCAMPage];
[RealPageAB, nRealPageAB] _ RWD[RPAccessA, busD, nBusD, RealPageAB, nRealPageAB, 24];
};
TRUSTED {
busD: SwitchMWord _ DESCRIPTOR[CAMBlock];
nBusD: SwitchMWord _ DESCRIPTOR[nCAMBlock];
[BlockAB, nBlockAB] _ RWW[BlockAccessA, busD, nBusD, BlockAB, nBlockAB, 4];
};

FOR i:quadIndex IN quadIndex DO
OPEN quadData[i];
IF NOT PhAb THEN MSelA _ FALSE;
IF PhAb AND EBFW[MQSelBA, 4, i] AND DataSelectA THEN MSelA _ TRUE;
IF PhAb AND RSelCellBA AND EBFW[MatchQSelBA, 4, i] AND ValidAB THEN nRQMatchA _ FALSE;
IF MSelA THEN {
[QMasterA, nQMasterA, Master, nMaster] _ RWB[MSelA, QMasterA, nQMasterA, Master, nMaster];
[QSharedA, nQSharedA, SharedAB, nSharedAB] _ RWB[MSelA, QSharedA, nQSharedA, SharedAB, nSharedAB];
[QValidA, nQValidA, ValidAB, nValidAB] _ RWB[MSelA, QValidA, nQValidA, ValidAB, nValidAB];
TRUSTED {
busD: SwitchMWord _ DESCRIPTOR[MBitsA];
nBusD: SwitchMWord _ DESCRIPTOR[nMBitsA];
dataFD: BitMWord _ DESCRIPTOR[Data[FALSE]];
dataTD: BitMWord _ DESCRIPTOR[Data[TRUE]];
RWM[MSelA, busD, nBusD, dataTD, dataFD, 132];
};
};
IF PhBb AND VSelCellAB AND SharedAB AND EBFW[PQSelAB, 4, i] THEN nQuadSharedB _ FALSE;
IF PhBb AND VictimSelectAB AND Master THEN nQDirtyB _ IBIW[FALSE, nQDirtyB, 4, i];
IF NOT PhBb THEN PSelB _ FALSE;
IF PhBb AND EBFW[PQSelAB, 4, i] AND VSelCellAB AND (nPStoreAB OR FinishSharedStoreAB OR (RPDirtyAB AND nSharedAB)) THEN PSelB _ TRUE;
IF PhBb AND EBFW[PQSelAB, 4, i] AND VSelCellAB AND ValidAB THEN nVQMatchB _ FALSE;
IF PSelB AND PStoreAB THEN {Master _ TRUE; nMaster _ FALSE};
IF PSelB THEN TRUSTED {
busD: SwitchMWord _ DESCRIPTOR[PBitsB];
nBusD: SwitchMWord _ DESCRIPTOR[nPBitsB];
dataFD: BitMWord _ DESCRIPTOR[Data[FALSE]];
dataTD: BitMWord _ DESCRIPTOR[Data[TRUE]];
RWM[PSelB, busD, nBusD, dataTD, dataFD, 132];
};
ENDLOOP;
IF NOT (quadData[0].MSelA OR quadData[1].MSelA OR quadData[2].MSelA OR quadData[3].MSelA) THEN TRUSTED {
dataD: BitMWord _ DESCRIPTOR[quadData[0].Data[FALSE]];
mBusD: SwitchMWord _ DESCRIPTOR[MBitsA];
nMBusD: SwitchMWord _ DESCRIPTOR[nMBitsA];
nQMasterA _ SIBISS[FALSE, nQMasterA, [[none, X], [none, X]]];
QMasterA _ SIBISS[FALSE, QMasterA, [[none, X], [none, X]]];
nQSharedA _ SIBISS[FALSE, nQSharedA, [[none, X], [none, X]]];
QSharedA _ SIBISS[FALSE, QSharedA, [[none, X], [none, X]]];
nQValidA _ SIBISS[FALSE, nQValidA, [[none, X], [none, X]]];
QValidA _ SIBISS[FALSE, QValidA, [[none, X], [none, X]]];
SCMTS[dataD, 132, 0, 132, nMBusD, 132, 0, 132, [[none, X], [none, X]]];
SCMTS[dataD, 132, 0, 132, mBusD, 132, 0, 132, [[none, X], [none, X]]];
};
IF NOT (quadData[0].PSelB OR quadData[1].PSelB OR quadData[2].PSelB OR quadData[3].PSelB) THEN TRUSTED {
dataD: BitMWord _ DESCRIPTOR[quadData[0].Data[FALSE]];
pBusD: SwitchMWord _ DESCRIPTOR[PBitsB];
nPBusD: SwitchMWord _ DESCRIPTOR[nPBitsB];
SCMTS[dataD, 132, 0, 132, nPBusD, 132, 0, 132, [[none, X], [none, X]]];
SCMTS[dataD, 132, 0, 132, pBusD, 132, 0, 132, [[none, X], [none, X]]];
};
Dragon.Assert[NOT Dragon.MoreThanOneOf[quadData[0].MSelA, quadData[1].MSelA, quadData[2].MSelA, quadData[3].MSelA]];
Dragon.Assert[NOT Dragon.MoreThanOneOf[quadData[0].PSelB, quadData[1].PSelB, quadData[2].PSelB, quadData[3].PSelB]];

hexVirtualPage _ ELFD[VirtualPageAB, 24, 0, 24];
hexRealPage _ ELFD[RealPageAB, 24, 0, 24];
hexBlock _ ELFW[BlockAB, 6, 0, 6];
TRUSTED {
assembleWord: BitDWord;
diff: BOOL _ FALSE;
FOR i:quadIndex IN quadIndex DO
IF oldMemBits[i]#quadData[i].Data[TRUE] THEN {diff _ TRUE; EXIT};
ENDLOOP;
IF diff OR ForceAllDataSelectsBA THEN FOR k:quadIndex IN quadIndex DO
FOR j:wordIndex IN wordIndex DO
desc: BitMWord _ DESCRIPTOR[quadData[k].Data[TRUE]];
FOR i:[0..32) IN [0..32) DO
assembleWord _ IBID[EBFM[desc, 132, (4*i)+j], assembleWord, 32, i];
ENDLOOP;
words[k][j] _ ELFD[assembleWord, 32, 0, 32];
parity[k][j] _ EBFM[desc, 132, 128+j];
ENDLOOP;
ENDLOOP;
}
ENDCELLTYPE


CacheEntry.rose
Last edited by: Barth, July 27, 1984 6:15:14 pm PDT
Last edited by: Curry, January 29, 1985 9:30:00 pm PST
Intermediate values, not state bits
Timing and housekeeping interface

Buffered timing and housekeeping interface

CAM interface
RAM access
Cell control
Cell to Cell
InitData
cellNumber: BitWord
Copy of virtualPage, realPage, block for easy display interpretation
Copy of data for easy display interpretation
Intermediate values, not state bits
Built into address decoder
Initializer
thisCellAdr _ cellNumber;
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