DIRECTORY
RoseTypes, RoseCreate, BitOps, BitSwOps, Dragon, SwitchTypes;

CacheEntry: CEDAR PROGRAM
IMPORTS RoseCreate, BitOps, BitSwOps, Dragon =

BEGIN OPEN
RoseTypes, BitOps, BitSwOps;



RegisterCells: PROC =
BEGIN
[] _ RoseCreate.RegisterCellType[name: "CacheEntry",
expandProc: NIL,
ioCreator: CreateCacheEntryIO, initializer: InitializeCacheEntry,
evals: [EvalSimple: CacheEntryEvalSimple],
blackBox: NIL, stateToo: NIL,
ports: CreateCacheEntryPorts[],
drivePrototype: NEW [CacheEntryDrive]];
END;
otherss: SymbolTable _ RoseCreate.GetOtherss["CacheEntry.pass"];

numberOfQuads: INT = 4;
numberOfWords: INT = 4;
numberOfEntries: INT = 4;
quadIndex: TYPE = [0..numberOfQuads);
wordIndex: TYPE = [0..numberOfWords);
memBits: TYPE = ARRAY [0..2*numberOfWords+1) OF BitWord;
QuadState: TYPE = RECORD[
Master, nMaster: BOOL,
SharedAB, nSharedAB: BOOL,
ValidAB, nValidAB: BOOL,
Data: ARRAY BOOLEAN OF memBits,
PSelB, MSelA: BOOL
];


CreateCacheEntryPorts: PROC RETURNS [ports: Ports] = {ports _ RoseCreate.PortsFromFile["CacheEntry.CacheEntry.rosePorts"]};

CacheEntryIORef: TYPE = REF CacheEntryIORec;
CacheEntryIORec: TYPE = MACHINE DEPENDENT RECORD [
fill0(0:0..14): [0..32767],
Vdd(0:15..15): BOOLEAN,
fill1(1:0..14): [0..32767],
Gnd(1:15..15): BOOLEAN,
fill2(2:0..14): [0..32767],
PhAb(2:15..15): BOOLEAN,
fill3(3:0..14): [0..32767],
PhBb(3:15..15): BOOLEAN,
CAMPage(4:0..383): PACKED ARRAY [0 .. 23] OF SwitchTypes.SwitchVal,
nCAMPage(28:0..383): PACKED ARRAY [0 .. 23] OF SwitchTypes.SwitchVal,
CAMBlock(52:0..63): PACKED ARRAY [0 .. 3] OF SwitchTypes.SwitchVal,
nCAMBlock(56:0..63): PACKED ARRAY [0 .. 3] OF SwitchTypes.SwitchVal,
PBitsB(60:0..2111): PACKED ARRAY [0 .. 131] OF SwitchTypes.SwitchVal,
nPBitsB(192:0..2111): PACKED ARRAY [0 .. 131] OF SwitchTypes.SwitchVal,
MBitsA(324:0..2111): PACKED ARRAY [0 .. 131] OF SwitchTypes.SwitchVal,
nMBitsA(456:0..2111): PACKED ARRAY [0 .. 131] OF SwitchTypes.SwitchVal,
fill12(588:0..14): [0..32767],
nVQMatchB(588:15..15): BOOLEAN,
fill13(589:0..14): [0..32767],
nQuadSharedB(589:15..15): BOOLEAN,
QValidA(590:0..15): SwitchTypes.SwitchVal,
nQValidA(591:0..15): SwitchTypes.SwitchVal,
QSharedA(592:0..15): SwitchTypes.SwitchVal,
nQSharedA(593:0..15): SwitchTypes.SwitchVal,
QMasterA(594:0..15): SwitchTypes.SwitchVal,
nQMasterA(595:0..15): SwitchTypes.SwitchVal,
fill20(596:0..11): [0..4095],
MQSelBA(596:12..15): [0..15],
fill21(597:0..11): [0..4095],
MatchQSelBA(597:12..15): [0..15],
fill22(598:0..14): [0..32767],
nRQMatchA(598:15..15): BOOLEAN,
fill23(599:0..14): [0..32767],
FinishSharedStoreAB(599:15..15): BOOLEAN,
fill24(600:0..11): [0..4095],
nQDirtyB(600:12..15): [0..15],
fill25(601:0..14): [0..32767],
PStoreAB(601:15..15): BOOLEAN,
fill26(602:0..14): [0..32767],
nPStoreAB(602:15..15): BOOLEAN,
fill27(603:0..11): [0..4095],
PQSelAB(603:12..15): [0..15],
fill28(604:0..14): [0..32767],
nPageDirtyB(604:15..15): BOOLEAN,
fill29(605:0..14): [0..32767],
nMapValidB(605:15..15): BOOLEAN,
RPValidBitA(606:0..15): SwitchTypes.SwitchVal,
nRPValidBitA(607:0..15): SwitchTypes.SwitchVal,
RPDirtyBitA(608:0..15): SwitchTypes.SwitchVal,
nRPDirtyBitA(609:0..15): SwitchTypes.SwitchVal,
VPValidBitA(610:0..15): SwitchTypes.SwitchVal,
nVPValidBitA(611:0..15): SwitchTypes.SwitchVal,
fill36(612:0..14): [0..32767],
ForceAllDataSelectsBA(612:15..15): BOOLEAN,
fill37(613:0..14): [0..32767],
nRealBlockMatchA(613:15..15): BOOLEAN,
fill38(614:0..14): [0..32767],
nVirtualBlockMatchB(614:15..15): BOOLEAN,
fill39(615:0..8): [0..511],
CellAdrBA(615:9..15): [0..127],
fill40(616:0..8): [0..511],
nCellAdrBA(616:9..15): [0..127],
fill41(617:0..14): [0..32767],
SenseRMatchB(617:15..15): BOOLEAN,
fill42(618:0..14): [0..32767],
SenseVictimA(618:15..15): BOOLEAN,
fill43(619:0..14): [0..32767],
SelOrphanAdrBA(619:15..15): BOOLEAN,
fill44(620:0..14): [0..32767],
SelMapAdrBA(620:15..15): BOOLEAN,
fill45(621:0..14): [0..32767],
SelVPBA(621:15..15): BOOLEAN,
fill46(622:0..14): [0..32767],
SelRPVictimBA(622:15..15): BOOLEAN,
fill47(623:0..14): [0..32767],
SelRPDecoderBA(623:15..15): BOOLEAN,
fill48(624:0..14): [0..32767],
SelRealDataBA(624:15..15): BOOLEAN,
fill49(625:0..14): [0..32767],
SelPageFlagsBA(625:15..15): BOOLEAN,
fill50(626:0..14): [0..32767],
SelDecodeBA(626:15..15): BOOLEAN,
fill51(627:0..14): [0..32767],
SenseVMatchA(627:15..15): BOOLEAN,
fill52(628:0..14): [0..32767],
DecodeSelectOutBA(628:15..15): BOOLEAN,
fill53(629:0..14): [0..32767],
DecodeSelectInBA(629:15..15): BOOLEAN];

CacheEntryCAMPagePortIndex: CARDINAL = 4;
CacheEntryNCAMPagePortIndex: CARDINAL = 5;
CacheEntryCAMBlockPortIndex: CARDINAL = 6;
CacheEntryNCAMBlockPortIndex: CARDINAL = 7;
CacheEntryPBitsBPortIndex: CARDINAL = 8;
CacheEntryNPBitsBPortIndex: CARDINAL = 9;
CacheEntryMBitsAPortIndex: CARDINAL = 10;
CacheEntryNMBitsAPortIndex: CARDINAL = 11;
CacheEntryQValidAPortIndex: CARDINAL = 14;
CacheEntryNQValidAPortIndex: CARDINAL = 15;
CacheEntryQSharedAPortIndex: CARDINAL = 16;
CacheEntryNQSharedAPortIndex: CARDINAL = 17;
CacheEntryQMasterAPortIndex: CARDINAL = 18;
CacheEntryNQMasterAPortIndex: CARDINAL = 19;
CacheEntryRPValidBitAPortIndex: CARDINAL = 30;
CacheEntryNRPValidBitAPortIndex: CARDINAL = 31;
CacheEntryRPDirtyBitAPortIndex: CARDINAL = 32;
CacheEntryNRPDirtyBitAPortIndex: CARDINAL = 33;
CacheEntryVPValidBitAPortIndex: CARDINAL = 34;
CacheEntryNVPValidBitAPortIndex: CARDINAL = 35;

CacheEntryDrive: TYPE = MACHINE DEPENDENT RECORD [
fill0(0:0..14): [0 .. 32768),
Vdd(0:15..15): BOOLEAN,
fill1(1:0..14): [0 .. 32768),
Gnd(1:15..15): BOOLEAN,
fill2(2:0..14): [0 .. 32768),
PhAb(2:15..15): BOOLEAN,
fill3(3:0..14): [0 .. 32768),
PhBb(3:15..15): BOOLEAN,
fill4(4:0..14): [0 .. 32768),
CAMPage(4:15..15): BOOLEAN,
fill5(5:0..14): [0 .. 32768),
nCAMPage(5:15..15): BOOLEAN,
fill6(6:0..14): [0 .. 32768),
CAMBlock(6:15..15): BOOLEAN,
fill7(7:0..14): [0 .. 32768),
nCAMBlock(7:15..15): BOOLEAN,
fill8(8:0..14): [0 .. 32768),
PBitsB(8:15..15): BOOLEAN,
fill9(9:0..14): [0 .. 32768),
nPBitsB(9:15..15): BOOLEAN,
fill10(10:0..14): [0 .. 32768),
MBitsA(10:15..15): BOOLEAN,
fill11(11:0..14): [0 .. 32768),
nMBitsA(11:15..15): BOOLEAN,
fill12(12:0..14): [0 .. 32768),
nVQMatchB(12:15..15): BOOLEAN,
fill13(13:0..14): [0 .. 32768),
nQuadSharedB(13:15..15): BOOLEAN,
fill14(14:0..14): [0 .. 32768),
QValidA(14:15..15): BOOLEAN,
fill15(15:0..14): [0 .. 32768),
nQValidA(15:15..15): BOOLEAN,
fill16(16:0..14): [0 .. 32768),
QSharedA(16:15..15): BOOLEAN,
fill17(17:0..14): [0 .. 32768),
nQSharedA(17:15..15): BOOLEAN,
fill18(18:0..14): [0 .. 32768),
QMasterA(18:15..15): BOOLEAN,
fill19(19:0..14): [0 .. 32768),
nQMasterA(19:15..15): BOOLEAN,
fill20(20:0..14): [0 .. 32768),
MQSelBA(20:15..15): BOOLEAN,
fill21(21:0..14): [0 .. 32768),
MatchQSelBA(21:15..15): BOOLEAN,
fill22(22:0..14): [0 .. 32768),
nRQMatchA(22:15..15): BOOLEAN,
fill23(23:0..14): [0 .. 32768),
FinishSharedStoreAB(23:15..15): BOOLEAN,
fill24(24:0..14): [0 .. 32768),
nQDirtyB(24:15..15): BOOLEAN,
fill25(25:0..14): [0 .. 32768),
PStoreAB(25:15..15): BOOLEAN,
fill26(26:0..14): [0 .. 32768),
nPStoreAB(26:15..15): BOOLEAN,
fill27(27:0..14): [0 .. 32768),
PQSelAB(27:15..15): BOOLEAN,
fill28(28:0..14): [0 .. 32768),
nPageDirtyB(28:15..15): BOOLEAN,
fill29(29:0..14): [0 .. 32768),
nMapValidB(29:15..15): BOOLEAN,
fill30(30:0..14): [0 .. 32768),
RPValidBitA(30:15..15): BOOLEAN,
fill31(31:0..14): [0 .. 32768),
nRPValidBitA(31:15..15): BOOLEAN,
fill32(32:0..14): [0 .. 32768),
RPDirtyBitA(32:15..15): BOOLEAN,
fill33(33:0..14): [0 .. 32768),
nRPDirtyBitA(33:15..15): BOOLEAN,
fill34(34:0..14): [0 .. 32768),
VPValidBitA(34:15..15): BOOLEAN,
fill35(35:0..14): [0 .. 32768),
nVPValidBitA(35:15..15): BOOLEAN,
fill36(36:0..14): [0 .. 32768),
ForceAllDataSelectsBA(36:15..15): BOOLEAN,
fill37(37:0..14): [0 .. 32768),
nRealBlockMatchA(37:15..15): BOOLEAN,
fill38(38:0..14): [0 .. 32768),
nVirtualBlockMatchB(38:15..15): BOOLEAN,
fill39(39:0..14): [0 .. 32768),
CellAdrBA(39:15..15): BOOLEAN,
fill40(40:0..14): [0 .. 32768),
nCellAdrBA(40:15..15): BOOLEAN,
fill41(41:0..14): [0 .. 32768),
SenseRMatchB(41:15..15): BOOLEAN,
fill42(42:0..14): [0 .. 32768),
SenseVictimA(42:15..15): BOOLEAN,
fill43(43:0..14): [0 .. 32768),
SelOrphanAdrBA(43:15..15): BOOLEAN,
fill44(44:0..14): [0 .. 32768),
SelMapAdrBA(44:15..15): BOOLEAN,
fill45(45:0..14): [0 .. 32768),
SelVPBA(45:15..15): BOOLEAN,
fill46(46:0..14): [0 .. 32768),
SelRPVictimBA(46:15..15): BOOLEAN,
fill47(47:0..14): [0 .. 32768),
SelRPDecoderBA(47:15..15): BOOLEAN,
fill48(48:0..14): [0 .. 32768),
SelRealDataBA(48:15..15): BOOLEAN,
fill49(49:0..14): [0 .. 32768),
SelPageFlagsBA(49:15..15): BOOLEAN,
fill50(50:0..14): [0 .. 32768),
SelDecodeBA(50:15..15): BOOLEAN,
fill51(51:0..14): [0 .. 32768),
SenseVMatchA(51:15..15): BOOLEAN,
fill52(52:0..14): [0 .. 32768),
DecodeSelectOutBA(52:15..15): BOOLEAN,
fill53(53:0..14): [0 .. 32768),
DecodeSelectInBA(53:15..15): BOOLEAN];


CreateCacheEntryIO: PROC [cell: Cell] --IOCreator-- = {
cell.realCellStuff.switchIO _ NEW [CacheEntryIORec];
cell.realCellStuff.newIO _ NEW [CacheEntryIORec];
cell.realCellStuff.oldIO _ NEW [CacheEntryIORec];
};

CacheEntryStateRef: TYPE = REF CacheEntryStateRec;
CacheEntryStateRec: TYPE = RECORD [
VPSelectAB, VBlSelectAB, RPSelectBA, RBlSelectBA, VictimSelectAB: BOOL,
VPValidAB, nVPValidAB: BOOL,
RPValidAB, nRPValidAB: BOOL,
RPDirtyAB, nRPDirtyAB: BOOL,
quadData: ARRAY quadIndex OF QuadState,
hexVirtualPage, hexRealPage, hexBlock: Dragon.HexWord,
words: ARRAY quadIndex OF ARRAY wordIndex OF Dragon.HexWord,
parity: ARRAY quadIndex OF ARRAY wordIndex OF BOOL,
VirtualPageAB, nVirtualPageAB: BitDWord,
RealPageAB, nRealPageAB: BitDWord,
BlockAB, nBlockAB: BitWord,
VSelMapAB, VSelCellAB, RSelMapBA, RSelCellBA: BOOL,
RPAccessA, BlockAccessA, VPAccessA, DataSelectA, FlagSelectA: BOOL,
thisCellAdr: BitWord
];

InitializeCacheEntry: Initializer = {
IF leafily THEN
BEGIN
state: CacheEntryStateRef _ NEW [CacheEntryStateRec];
cell.realCellStuff.state _ state;
END;
};

CacheEntryEvalSimple: CellProc =
BEGIN
sw: CacheEntryIORef _ NARROW[cell.realCellStuff.switchIO];
newIO: CacheEntryIORef _ NARROW[cell.realCellStuff.newIO];
state: CacheEntryStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN newIO, state;
oldMemBits: ARRAY quadIndex OF memBits;

RWB: PROC [access: BOOL, bus, nBus: Switch, bit, nbit: BOOL] RETURNS [newBus, nNewBus: Switch, newBit, newnBit: BOOL] = {
s: SwitchTypes.Strength _ IF access THEN drive ELSE none;
IF access THEN {
bit _ (NOT nbit) AND bus.val=H;
nbit _ (NOT bit) AND nBus.val=H;
bit _ (NOT nbit) AND bus.val=H;
};
nNewBus _ SIBISS[bit, nBus, [[none, X], [s, L]]];
newBus _ SIBISS[nbit, bus, [[none, X], [s, L]]];
newBit _ bit;
newnBit _ nbit;
};

RWW: PROC [access: BOOL, busD, nBusD: SwitchMWord, field, nfield: BitWord, fieldWidth: CARDINAL] RETURNS [newField, newnField: BitWord] = TRUSTED {
s: SwitchTypes.Strength _ IF access THEN drive ELSE none;
IF access THEN FOR i:CARDINAL IN [0..fieldWidth) DO
field _ IBIW[(NOT EBFW[nfield, fieldWidth, i]) AND busD[i].val=H, field, fieldWidth, i];
nfield _ IBIW[(NOT EBFW[field, fieldWidth, i]) AND nBusD[i].val=H, nfield, fieldWidth, i];
field _ IBIW[(NOT EBFW[nfield, fieldWidth, i]) AND busD[i].val=H, field, fieldWidth, i];
ENDLOOP;
SCWTS[field, fieldWidth, 0, fieldWidth, nBusD, fieldWidth, 0, fieldWidth, [[none, X], [s, L]]];
SCWTS[nfield, fieldWidth, 0, fieldWidth, busD, fieldWidth, 0, fieldWidth, [[none, X], [s, L]]];
newField _ field;
newnField _ nfield;
};

RWD: PROC [access: BOOL, busD, nBusD: SwitchMWord, field, nfield: BitDWord, fieldWidth: CARDINAL] RETURNS [newField, newnField: BitDWord] = TRUSTED {
s: SwitchTypes.Strength _ IF access THEN drive ELSE none;
IF access THEN FOR i:CARDINAL IN [0..fieldWidth) DO
field _ IBID[(NOT EBFD[nfield, fieldWidth, i]) AND busD[i].val=H, field, fieldWidth, i];
nfield _ IBID[(NOT EBFD[field, fieldWidth, i]) AND nBusD[i].val=H, nfield, fieldWidth, i];
field _ IBID[(NOT EBFD[nfield, fieldWidth, i]) AND busD[i].val=H, field, fieldWidth, i];
ENDLOOP;
SCDTS[field, fieldWidth, 0, fieldWidth, nBusD, fieldWidth, 0, fieldWidth, [[none, X], [s, L]]];
SCDTS[nfield, fieldWidth, 0, fieldWidth, busD, fieldWidth, 0, fieldWidth, [[none, X], [s, L]]];
newField _ field;
newnField _ nfield;
};

RWM: PROC [access: BOOL, busD, nBusD: SwitchMWord, field, nfield: BitMWord, fieldWidth: CARDINAL] = TRUSTED {
s: SwitchTypes.Strength _ IF access THEN drive ELSE none;
IF access THEN FOR i:CARDINAL IN [0..fieldWidth) DO
IBIM[(NOT EBFM[nfield, fieldWidth, i]) AND busD[i].val=H, field, fieldWidth, i];
IBIM[(NOT EBFM[field, fieldWidth, i]) AND nBusD[i].val=H, nfield, fieldWidth, i];
IBIM[(NOT EBFM[nfield, fieldWidth, i]) AND busD[i].val=H, field, fieldWidth, i];
ENDLOOP;
SCMTS[field, fieldWidth, 0, fieldWidth, nBusD, fieldWidth, 0, fieldWidth, [[none, X], [s, L]]];
SCMTS[nfield, fieldWidth, 0, fieldWidth, busD, fieldWidth, 0, fieldWidth, [[none, X], [s, L]]];
};

FOR i:quadIndex IN quadIndex DO
oldMemBits[i] _ quadData[i].Data[TRUE];
ENDLOOP;

TRUSTED {
cp: BitDWord _ CSTD[DESCRIPTOR[CAMPage], 24, 0, 24, BitDWordZero, 24, 0, 24];
ncp: BitDWord _ CSTD[DESCRIPTOR[nCAMPage], 24, 0, 24, BitDWordZero, 24, 0, 24];
cb: BitWord _ CSTW[DESCRIPTOR[CAMBlock], 4, 0, 4, 0, 4, 0, 4];
ncb: BitWord _ CSTW[DESCRIPTOR[nCAMBlock], 4, 0, 4, 0, 4, 0, 4];
IF SenseVMatchA THEN {
VPSelectAB _ DAND[ncp, VirtualPageAB]=BitDWordZero AND DAND[cp, nVirtualPageAB]=BitDWordZero;
VBlSelectAB _ WAND[ncb, BlockAB]=0 AND WAND[cb, nBlockAB]=0;
};
IF SenseRMatchB THEN {
RPSelectBA _ DAND[ncp, RealPageAB]=BitDWordZero AND DAND[cp, nRealPageAB]=BitDWordZero;
RBlSelectBA _ WAND[ncb, BlockAB]=0 AND WAND[cb, nBlockAB]=0;
};
};
VSelMapAB _ VPValidAB AND VPSelectAB;
VSelCellAB _ VSelMapAB AND VBlSelectAB;
RSelMapBA _ RPValidAB AND RPSelectBA;
RSelCellBA _ RSelMapBA AND RBlSelectBA;
IF VSelMapAB AND PhBb THEN {
nMapValidB _ FALSE;
IF RPDirtyAB THEN nPageDirtyB _ FALSE;
};
IF VSelCellAB AND PhBb THEN nVirtualBlockMatchB _ FALSE;
IF RSelCellBA AND PhAb THEN nRealBlockMatchA _ FALSE;
DecodeSelectOutBA _ CellAdrBA=thisCellAdr AND CellAdrBA=WNOT[nCellAdrBA, 7];
IF SenseVictimA THEN VictimSelectAB _ DecodeSelectInBA;
IF NOT PhAb THEN {
RPAccessA _ FALSE;
BlockAccessA _ FALSE;
VPAccessA _ FALSE;
DataSelectA _ FALSE;
FlagSelectA _ FALSE;
};
IF PhAb THEN {
IF (SelMapAdrBA AND VSelMapAB) OR (SelRPDecoderBA AND DecodeSelectOutBA) OR (SelRPVictimBA AND VictimSelectAB) THEN RPAccessA _ TRUE;
IF (SelRPDecoderBA AND DecodeSelectOutBA) OR (SelRPVictimBA AND VictimSelectAB) THEN BlockAccessA _ TRUE;
IF (SelOrphanAdrBA AND RSelCellBA) OR (SelVPBA AND DecodeSelectOutBA) THEN VPAccessA _ TRUE;
IF (SelRealDataBA AND RSelCellBA) OR (DecodeSelectOutBA AND SelDecodeBA) OR ForceAllDataSelectsBA THEN DataSelectA _ TRUE;
IF (SelPageFlagsBA AND RSelMapBA) OR DataSelectA THEN FlagSelectA _ TRUE;
};
[RPValidBitA, nRPValidBitA, RPValidAB, nRPValidAB] _ RWB[DataSelectA, RPValidBitA, nRPValidBitA, RPValidAB, nRPValidAB];
[RPDirtyBitA, nRPDirtyBitA, RPDirtyAB, nRPDirtyAB] _ RWB[FlagSelectA, RPDirtyBitA, nRPDirtyBitA, RPDirtyAB, nRPDirtyAB];
[VPValidBitA, nVPValidBitA, VPValidAB, nVPValidAB] _ RWB[FlagSelectA, VPValidBitA, nVPValidBitA, VPValidAB, nVPValidAB];
TRUSTED {
busD: SwitchMWord _ DESCRIPTOR[CAMPage];
nBusD: SwitchMWord _ DESCRIPTOR[nCAMPage];
[VirtualPageAB, nVirtualPageAB] _ RWD[VPAccessA, busD, nBusD, VirtualPageAB, nVirtualPageAB, 24];
};
TRUSTED {
busD: SwitchMWord _ DESCRIPTOR[CAMPage];
nBusD: SwitchMWord _ DESCRIPTOR[nCAMPage];
[RealPageAB, nRealPageAB] _ RWD[RPAccessA, busD, nBusD, RealPageAB, nRealPageAB, 24];
};
TRUSTED {
busD: SwitchMWord _ DESCRIPTOR[CAMBlock];
nBusD: SwitchMWord _ DESCRIPTOR[nCAMBlock];
[BlockAB, nBlockAB] _ RWW[BlockAccessA, busD, nBusD, BlockAB, nBlockAB, 4];
};

FOR i:quadIndex IN quadIndex DO
OPEN quadData[i];
IF NOT PhAb THEN MSelA _ FALSE;
IF PhAb AND EBFW[MQSelBA, 4, i] AND DataSelectA THEN MSelA _ TRUE;
IF PhAb AND RSelCellBA AND EBFW[MatchQSelBA, 4, i] AND ValidAB THEN nRQMatchA _ FALSE;
IF MSelA THEN {
[QMasterA, nQMasterA, Master, nMaster] _ RWB[MSelA, QMasterA, nQMasterA, Master, nMaster];
[QSharedA, nQSharedA, SharedAB, nSharedAB] _ RWB[MSelA, QSharedA, nQSharedA, SharedAB, nSharedAB];
[QValidA, nQValidA, ValidAB, nValidAB] _ RWB[MSelA, QValidA, nQValidA, ValidAB, nValidAB];
TRUSTED {
busD: SwitchMWord _ DESCRIPTOR[MBitsA];
nBusD: SwitchMWord _ DESCRIPTOR[nMBitsA];
dataFD: BitMWord _ DESCRIPTOR[Data[FALSE]];
dataTD: BitMWord _ DESCRIPTOR[Data[TRUE]];
RWM[MSelA, busD, nBusD, dataTD, dataFD, 132];
};
};
IF PhBb AND VSelCellAB AND SharedAB AND EBFW[PQSelAB, 4, i] THEN nQuadSharedB _ FALSE;
IF PhBb AND VictimSelectAB AND Master THEN nQDirtyB _ IBIW[FALSE, nQDirtyB, 4, i];
IF NOT PhBb THEN PSelB _ FALSE;
IF PhBb AND EBFW[PQSelAB, 4, i] AND VSelCellAB AND (nPStoreAB OR FinishSharedStoreAB OR (RPDirtyAB AND nSharedAB)) THEN PSelB _ TRUE;
IF PhBb AND EBFW[PQSelAB, 4, i] AND VSelCellAB AND ValidAB THEN nVQMatchB _ FALSE;
IF PSelB AND PStoreAB THEN {Master _ TRUE; nMaster _ FALSE};
IF PSelB THEN TRUSTED {
busD: SwitchMWord _ DESCRIPTOR[PBitsB];
nBusD: SwitchMWord _ DESCRIPTOR[nPBitsB];
dataFD: BitMWord _ DESCRIPTOR[Data[FALSE]];
dataTD: BitMWord _ DESCRIPTOR[Data[TRUE]];
RWM[PSelB, busD, nBusD, dataTD, dataFD, 132];
};
ENDLOOP;
IF NOT (quadData[0].MSelA OR quadData[1].MSelA OR quadData[2].MSelA OR quadData[3].MSelA) THEN TRUSTED {
dataD: BitMWord _ DESCRIPTOR[quadData[0].Data[FALSE]];
mBusD: SwitchMWord _ DESCRIPTOR[MBitsA];
nMBusD: SwitchMWord _ DESCRIPTOR[nMBitsA];
nQMasterA _ SIBISS[FALSE, nQMasterA, [[none, X], [none, X]]];
QMasterA _ SIBISS[FALSE, QMasterA, [[none, X], [none, X]]];
nQSharedA _ SIBISS[FALSE, nQSharedA, [[none, X], [none, X]]];
QSharedA _ SIBISS[FALSE, QSharedA, [[none, X], [none, X]]];
nQValidA _ SIBISS[FALSE, nQValidA, [[none, X], [none, X]]];
QValidA _ SIBISS[FALSE, QValidA, [[none, X], [none, X]]];
SCMTS[dataD, 132, 0, 132, nMBusD, 132, 0, 132, [[none, X], [none, X]]];
SCMTS[dataD, 132, 0, 132, mBusD, 132, 0, 132, [[none, X], [none, X]]];
};
IF NOT (quadData[0].PSelB OR quadData[1].PSelB OR quadData[2].PSelB OR quadData[3].PSelB) THEN TRUSTED {
dataD: BitMWord _ DESCRIPTOR[quadData[0].Data[FALSE]];
pBusD: SwitchMWord _ DESCRIPTOR[PBitsB];
nPBusD: SwitchMWord _ DESCRIPTOR[nPBitsB];
SCMTS[dataD, 132, 0, 132, nPBusD, 132, 0, 132, [[none, X], [none, X]]];
SCMTS[dataD, 132, 0, 132, pBusD, 132, 0, 132, [[none, X], [none, X]]];
};
Dragon.Assert[NOT Dragon.MoreThanOneOf[quadData[0].MSelA, quadData[1].MSelA, quadData[2].MSelA, quadData[3].MSelA]];
Dragon.Assert[NOT Dragon.MoreThanOneOf[quadData[0].PSelB, quadData[1].PSelB, quadData[2].PSelB, quadData[3].PSelB]];

hexVirtualPage _ ELFD[VirtualPageAB, 24, 0, 24];
hexRealPage _ ELFD[RealPageAB, 24, 0, 24];
hexBlock _ ELFW[BlockAB, 6, 0, 6];
TRUSTED {
assembleWord: BitDWord;
diff: BOOL _ FALSE;
FOR i:quadIndex IN quadIndex DO
IF oldMemBits[i]#quadData[i].Data[TRUE] THEN {diff _ TRUE; EXIT};
ENDLOOP;
IF diff OR ForceAllDataSelectsBA THEN FOR k:quadIndex IN quadIndex DO
FOR j:wordIndex IN wordIndex DO
desc: BitMWord _ DESCRIPTOR[quadData[k].Data[TRUE]];
FOR i:[0..32) IN [0..32) DO
assembleWord _ IBID[EBFM[desc, 132, (4*i)+j], assembleWord, 32, i];
ENDLOOP;
words[k][j] _ ELFD[assembleWord, 32, 0, 32];
parity[k][j] _ EBFM[desc, 132, 128+j];
ENDLOOP;
ENDLOOP;
}
END;
END;

RegisterCells[];

END.

¨CacheEntry.Mesa
created by RoseTranslate from CacheEntry.Rose of February 1, 1985 9:26:56 am PST for curry.pa at February 1, 1985 9:27:15 am PST
Signal Type decls
explicitly requested CEDAR:
Intermediate values, not state bits
port indices:
Copy of virtualPage, realPage, block for easy display interpretation
Copy of data for easy display interpretation
Intermediate values, not state bits
Built into address decoder
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