CacheTesterA.mesa
Last Edited by: Barth, July 26, 1984 7:19:04 pm PDT
DIRECTORY Cache, CacheTester, CacheTesterB, Process;
CacheTesterA: CEDAR PROGRAM
IMPORTS Cache, CacheTester, CacheTesterB, Process
SHARES Cache, CacheTester, CacheTesterB =
BEGIN OPEN CacheTester, CacheTesterB;
CacheTest: Cache.CacheTester = {
priority: Process.Priority ← Process.GetPriority[];
clocksSkewed ← FALSE;
{
Process.SetPriority[Process.priorityBackground];
ReallyCacheTest[i, d, h
! UNWIND => Process.SetPriority[priority];
EtuBrute => GOTO quit];
EXITS
quit => NULL;
};
Process.SetPriority[priority];
IF clocksSkewed THEN Complain["clocks out of sync"];
};
ReallyCacheTest: Cache.CacheTester = {
OPEN value;
clockPhase ← 3;
cycleNumber ← 0;
pushWaitCount ← 0;
evalWaitCount ← 0;
evalCount ← 0;
drive ← d;
instructions ← i;
handle ← h;
killThreads ← FALSE;
ignoreWarnings ← FALSE;
Invariant: Each thread always calls P before changing anything in value or drive. All threads must have called P before P actually advances the clock and lets the evaluation procede. E only executes when all threads are hung on P or E.
UNTIL threadCount=0 DO
Process.Yield[];
ENDLOOP;
PhA ← FALSE;
PhB ← FALSE;
ThreadStart[MainThread];
UNTIL threadCount=0 DO
EntryEval[];
ENDLOOP;
};
MainThread: ThreadProc = {
OPEN value;
DoAReset[];
ThreadStart[MCommand, NEW[MCommandRec ← [slave: TRUE, wqCount: 1, wqData: [[WQAddress: 0, WQData0: 1, WQData1: 2, WQData2: 3, WQData3: 4],,,]]]];
C[5];
ThreadStart[MCommand, NEW[MCommandRec ← [slave: TRUE, RQ: TRUE, RQAddress: 5, RQData0: 6, RQData1: 7, RQData2: 8, RQData3: 9]]];
C[6];
ThreadStart[MCommand, NEW[MCommandRec ← [slave: TRUE, WS: TRUE, WSAddress: 10, WSData: 11]]];
C[2];
ThreadStart[MCommand, NEW[MCommandRec ← [slave: TRUE, CF: TRUE, CFData: 12]]];
C[2];
ThreadStart[PReference, NEW[PReferenceRec ← [command: IOFetchHold, address: 2, data: 00060001H, rejects: 5]]];
ThreadStart[MCommand, NEW[MCommandRec ← [arb: TRUE, releaseBus: FALSE, IOR: TRUE, IOAddress: 2, IOData: 00060001H]]];
C[8];
ThreadStart[PReference, NEW[PReferenceRec ← [command: IOStoreHold, address: 3, data: 00070001H, rejects: 4]]];
C[2];
ThreadStart[MCommand, NEW[MCommandRec ← [releaseBus: FALSE, IOW: TRUE, IOAddress: 3, IOData: 00070001H]]];
C[5];
ThreadStart[PReference, NEW[PReferenceRec ← [command: IOFetch, address: 4, data: 00080001H, rejects: 4]]];
C[2];
ThreadStart[MCommand, NEW[MCommandRec ← [IOR: TRUE, IOAddress: 4, IOData: 00080001H]]];
C[5];
P[A]; drive.MCmdAB ← TRUE; MCmdAB ← NoOp; MNShared ← TRUE; F[]; drive.MCmdAB ← FALSE;
ThreadStart[PReference, NEW[PReferenceRec ← [command: Store, address: 1, data: 2, rejects: 17]]];
ThreadStart[MCommand, NEW[MCommandRec ← [arb: TRUE, IOR: TRUE, IOAddress: 0C0H, IOData:00010000H, RQ: TRUE, rqNotReadyCount: 2, rqShared: TRUE, RQAddress:00010001H, RQData0: 00020001H, RQData1: 00020002H, RQData2: 00020003H, RQData3: 00020004H, WS: TRUE, WSAddress:00010001H, WSData:02H]]];
C[18];
P[A]; drive.MCmdAB ← TRUE; MCmdAB ← NoOp; MNShared ← TRUE; F[]; drive.MCmdAB ← FALSE;
ThreadStart[PReference, NEW[PReferenceRec ← [command: Fetch, address: 1, data: 2]]]; C[];
ThreadStart[PReference, NEW[PReferenceRec ← [command: Fetch, address: 0, data: 00020004H]]]; C[];
ThreadStart[PReference, NEW[PReferenceRec ← [command: Fetch, address: 2, data: 00020002H]]]; C[];
ThreadStart[PReference, NEW[PReferenceRec ← [command: Fetch, address: 3, data: 00020003H]]]; C[];
ThreadStart[PReference, NEW[PReferenceRec ← [command: Fetch, address: 4, data: 00040000H, rejects: 6]]];
ThreadStart[MCommand, NEW[MCommandRec ← [arb: TRUE, RQ: TRUE, RQAddress:00010004H, RQData0: 00040000H, RQData1: 00040001H, RQData2: 00040002H, RQData3: 00040003H]]];
C[9];
P[A]; drive.MCmdAB ← TRUE; MCmdAB ← NoOp; MNShared ← TRUE; F[]; drive.MCmdAB ← FALSE;
ThreadStart[PReference, NEW[PReferenceRec ← [command: FetchHold, address: 6, data: 00040002H, rejects: 3]]];
ThreadStart[MCommand, NEW[MCommandRec ← [arb: TRUE, releaseBus: FALSE]]];
C[4];
ThreadStart[PReference, NEW[PReferenceRec ← [command: Store, address: 6, data: 00040012H]]];
C[];
ThreadStart[PReference, NEW[PReferenceRec ← [command: StoreHold, address: 6, data: 00040112H, rejects: 3]]];
ThreadStart[MCommand, NEW[MCommandRec ← [arb: TRUE, newRequest: TRUE, releaseBus: FALSE]]];
drive.MCmdAB ← TRUE; MCmdAB ← Reserve14; E[]; drive.MCmdAB ← FALSE;
P[A]; MCmdAB ← NoOp; F[];
C[4];
ThreadStart[PReference, NEW[PReferenceRec ← [command: Fetch, address: 6, data: 00040112H]]];
C[];
ThreadStart[MCommand, NEW[MCommandRec ← []]];
C[3];
P[A]; drive.MCmdAB ← TRUE; MCmdAB ← NoOp; MNShared ← TRUE; E[]; drive.MCmdAB ← FALSE; F[];
ThreadStart[PReference, NEW[PReferenceRec ← [command: Fetch, address: 10H, data: 00080000H, rejects: 6]]];
ThreadStart[MCommand, NEW[MCommandRec ← [arb: TRUE, RQ: TRUE, RQAddress:00010010H, RQData0: 00080000H, RQData1: 00080001H, RQData2: 00080002H, RQData3: 00080003H]]];
C[9];
P[A]; drive.MCmdAB ← TRUE; MCmdAB ← NoOp; E[]; drive.MCmdAB ← FALSE; F[];
ThreadStart[PReference, NEW[PReferenceRec ← [command: Fetch, address: 20H, data: 00200000H, rejects: 6]]];
ThreadStart[MCommand, NEW[MCommandRec ← [arb: TRUE, RQ: TRUE, RQAddress:00010020H, RQData0: 00200000H, RQData1: 00200001H, RQData2: 00200002H, RQData3: 00200003H]]];
C[9];
P[A]; drive.MCmdAB ← TRUE; MCmdAB ← NoOp; E[]; drive.MCmdAB ← FALSE; F[];
ThreadStart[PReference, NEW[PReferenceRec ← [command: Fetch, address: 30H, data: 00300000H, rejects: 6]]];
ThreadStart[MCommand, NEW[MCommandRec ← [arb: TRUE, RQ: TRUE, RQAddress:00010030H, RQData0: 00300000H, RQData1: 00300001H, RQData2: 00300002H, RQData3: 00300003H]]];
C[9];
P[A]; drive.MCmdAB ← TRUE; MCmdAB ← NoOp; E[]; drive.MCmdAB ← FALSE; F[];
ThreadStart[PReference, NEW[PReferenceRec ← [command: Fetch, address: 40H, data: 00400000H, rejects: 19]]];
ThreadStart[MCommand, NEW[MCommandRec ← [arb: TRUE, wqCount: 2, wqData: [[wqNotReadyCount: 3, WQAddress: 00010000H, WQData0: 00020004H, WQData1: 00000002H, WQData2: 00020002H, WQData3: 00020003H], [WQAddress: 00010004H, WQData0: 00040000H, WQData1: 00040001H, WQData2: 00040112H, WQData3: 00040003H],,], RQ: TRUE, RQAddress:00010040H, RQData0: 00400000H, RQData1: 00400001H, RQData2: 00400002H, RQData3: 00400003H]]];
C[22];
P[A]; drive.MCmdAB ← TRUE; MCmdAB ← NoOp; E[]; drive.MCmdAB ← FALSE; F[];
ThreadStart[PReference, NEW[PReferenceRec ← [command: Fetch, address: 50H, data: 00500000H, rejects: 6]]];
ThreadStart[MCommand, NEW[MCommandRec ← [arb: TRUE, RQ: TRUE, RQAddress:00010050H, RQData0: 00500000H, RQData1: 00500001H, RQData2: 00500002H, RQData3: 00500003H]]];
C[9];
P[A]; drive.MCmdAB ← TRUE; MCmdAB ← NoOp; E[]; drive.MCmdAB ← FALSE; F[];
Chunk1[];
};
Cache.RegisterCacheTester[CacheTest];
END.
The following note is not up to date !!!
Bits in the debug shift register in order of appearance. Put them in and read them out backwards! Multiple bit quantities within CacheMx appear low order bit first, within CachePx appear high order bit first. There is currently a total of 33+1+8+26+12+0+30+30+12+33+1 or 186 bits.
CacheMRAMDriver 33
shiftDataParity
shiftData[32]
CacheMCtlRAMCtl 1
shiftHighAddress
CacheMCtlFlagCtl 8
sVPValid
sRPValid
sRPDirty
sMaster
sShared
sVictim
sTIP
sBroken
CacheMCtlSequencer 26
cycleShifterAB[7]
currentSequenceAB[7]
currentPDemandsBA[7]
slaveAB
forceSlaveBA
wonArbitrationAB
mWantsMBA
samplePDemandsBA
CacheMCtlEntryCtl 12
sMAdrLow
sMAdrHigh
sReadEntry
sWriteEntry
sCellAdr[8]
CacheMCtlCAMCtl 0
CacheMCAMDriver 30
shiftData[30]
CachePCAMDriver 30
shiftData[30]
CachePCtl 12
loadEnable
loadMustBeOne
pCmdShift[4]
rejectShift
parityShift
requestShift
readVA
pAdrLowShift
pAdrHighShift
CachePRAMDriver 33
shiftData[32]
parityShift
CacheMPads 1
shiftAB